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Sun, 30 Aug 2026 23:00:38 -0700 (PDT) X-Received: by 2002:a17:903:1b67:b0:2d8:d4d1:313e with SMTP id d9443c01a7336-2d8d4d14b8amr226894885ad.21.1788156035118; Sun, 30 Aug 2026 23:00:35 -0700 (PDT) Received: from [10.218.26.96] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2d75986aec6sm28746735ad.48.2026.08.30.23.00.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 30 Aug 2026 23:00:34 -0700 (PDT) Message-ID: <311cf38a-1af5-46fe-b2a7-4ea32c17d59e@oss.qualcomm.com> Date: Mon, 31 Aug 2026 11:30:28 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 00/11] arm64: dts: qcom: Disable Inline Crypto Engine by default accross all SoCs To: Kuldeep Singh , Abel Vesa , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , cros-qcom-dts-watchers@chromium.org Cc: Konrad Dybcio , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260828-b4-dts-qcom-disable-ice-by-default-v1-0-1d6e0c2f5a69@oss.qualcomm.com> <53a855e1-5d5e-46bf-86e9-d605c57312f8@oss.qualcomm.com> Content-Language: en-US From: Harshal Dev Organization: Qualcomm In-Reply-To: <53a855e1-5d5e-46bf-86e9-d605c57312f8@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDA0OSBTYWx0ZWRfX+sJoO0Oipmcu /dnKIeH/2KqRULdA6qZa3v0bl+pzrjZyCuFcDWhqll4MJJEUhVmF1hxLASyqQ4xdAUEB8ulUX8T LBNQ9Ym3bVwdprSBkqpz+whBspaUQ4NIw8Mey3k1LekjrsomlmRaY3zEnfbkZRjH/U0t9WaK+TE Vg+2BWtvXMXyd8g7wF1fQMGSG8qnL/7ketKcAnjZr9IV88oFjgLskIv/hNWYHOq8kzhioHn5Q/I aNqGEZ4hjcknfzuPNuDP63tmZ7+fSYf7kes5O7gRA12mR/STgvvdpFryn4mT79H04XqYi4ONINX AIEEHmaUpbtpf+U6mEOZyMH0E60Fgnqm8fe916Zlb97jaUK4Z2yztyjDzPyL1N0oqOquPvGt2// c+07oShx+Q5op6qpGQuoJ0+EUU2rtj5aUcqp/jCqaRfTazZfjTc94dHUXDObYYuGGK+fdalHyKw suA3PEmUu1MT5UlEYuQ== X-Proofpoint-GUID: obifmeEQCA-8Tt9_fFRgx5mKZ5sHcnul X-Authority-Analysis: v=2.4 cv=Zakt8MVA c=1 sm=1 tr=0 ts=6a951888 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=ZHziGR1QICH9RQWzh8IA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDA0OSBTYWx0ZWRfX3pFUDjQNuJMk V2UvlP0KkT68DLu+royfdvGf6aQjyk3Rz+BSBLjqu+NMNyKBFd+VuDh0pt++E1LUCCxAU5A9YGL u9x46ozS5FUgAwA9HUF5bmFsc1fdN18= X-Proofpoint-ORIG-GUID: obifmeEQCA-8Tt9_fFRgx5mKZ5sHcnul X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_02,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 phishscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 spamscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310049 Hi Abel On 28-08-2026 06:17 pm, Kuldeep Singh wrote: > > > On 28-08-2026 18:07, Abel Vesa wrote: >> Since UFS_PHY_GDSC was attached to the Inline Crypto Engine and the driver >> does not currently do runtime PM, the GDSC remains enabled while the >> device is idle, even on boards where there are no consumers. >> >> I'm working on getting runtime PM enabled in the ICE driver, but the >> node should not be enabled on such boards anyways. >> >> So disable the Inline Crypto Engine by default in the SoC DTSI and enable >> it only in board DTS files that use it. >> >> Do this accross the board, for all SoCs that have dedicated ICE DT node. >> >> Signed-off-by: Abel Vesa > > Kindly check discussion happenend before on adding such implementation. > > https://lore.kernel.org/all/56ab63c3-4288-45f7-bfea-d40046437a9f@oss.qualcomm.com/ > > The idea is to enable ice as default and independent of storage media > and enable runtime PM enabled. > I agree with the discussion and Konrad's point on the referenced thread. It makes more sense to put efforts into runtime PM for ICE instead of disabling it by default on all SoCs. This series brings the obvious overhead of having to send patches for every new board added upstream that requires ICE. Also, once we have runtime PM enabled, we would not needed these board-specific enablement changes anyways. Regards, Harshal