From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DB28B39D3C0 for ; Mon, 1 Jun 2026 09:53:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780307631; cv=none; b=VCB2WI9XH/KV2duLWe+rU0RcBT3GslSzj+cEcLY5CVGSgA8aJ/OIUxrDR+J4kdzaCyprjMUe1HI+tsgx+xrWtgGN5oaIS3kiUtV1sPBQoMwlR06BZnVsHz5QvTP15TN8SanD/ZpQcIGEl+YmMxLUF2goHSZUS/UGbBOwh9j0ttM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780307631; c=relaxed/simple; bh=Pe2ZlJy8oKAD/VulpHzRR75gUtJV5sCF9VpBEoEx/k4=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=qcFqpA7Hd38Q736uyaH44HlmpZcFne9i6FuNZAGofjK7sMxD8nxqgOg8MHC+hVWJC9x45v1Un6ZwCLTfwK++vV60Opb+x2gjwKLVnOh4IxHuQkk92frJxddY85DAUHGScN/ZyOKcYDZ4K/1oSMGu+gnn+XMnrE7Db0K/h3rXuyI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=kEScZh6U; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="kEScZh6U" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1AFF81E8D; Mon, 1 Jun 2026 02:53:36 -0700 (PDT) Received: from [10.1.38.31] (Suzukis-MBP.cambridge.arm.com [10.1.38.31]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E7E213F905; Mon, 1 Jun 2026 02:53:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1780307621; bh=Pe2ZlJy8oKAD/VulpHzRR75gUtJV5sCF9VpBEoEx/k4=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=kEScZh6UoN7ivaCz/gpnJZG+S6y9uAXQioLOL1RBUVEwiGpvDq1PuYJG3JNnh0VHx ipdlAv2rtKj/vQJ5Oz48p0C5NDcP+m90ysqeQk1ChdpDq/dnuWCK/H3VpSUZ1KP/3f T+A2rEfRSe1CIXDcFxp84Rj8MJ1PnRLSKDnUASec= Message-ID: <3144c7fb-b41d-4bca-a6a0-eeb9dfddc8b8@arm.com> Date: Mon, 1 Jun 2026 10:53:38 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 03/13] coresight: etm4x: introduce ETM_MAX_SEQ_TRANSITIONS Content-Language: en-GB To: Yeoreum Yun , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mike.leach@arm.com, james.clark@linaro.org, alexander.shishkin@linux.intel.com, leo.yan@arm.com, jie.gan@oss.qualcomm.com References: <20260519154812.254884-1-yeoreum.yun@arm.com> <20260519154812.254884-4-yeoreum.yun@arm.com> From: Suzuki K Poulose In-Reply-To: <20260519154812.254884-4-yeoreum.yun@arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 19/05/2026 16:48, Yeoreum Yun wrote: > According to IHI006H Embedded Trace Macrocell Architecture > Specification [0], n could be 0-2 for TCRSEQEVR when > TCRIDR5.NUMSEQSTATE is 0b100. > > Therefore, introduce ETM_MAX_SEQ_TRANSITIONS macro and apply this > in TCRSEQEVR relevant fields. > > Link: https://developer.arm.com/documentation/ihi0064/latest/ [0] > Suggestedby: Leo Yan > Signed-off-by: Yeoreum Yun > --- > drivers/hwtracing/coresight/coresight-etm4x-cfg.c | 2 +- > drivers/hwtracing/coresight/coresight-etm4x.h | 5 +++-- > 2 files changed, 4 insertions(+), 3 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c > index c302072b293a..e1a59b434505 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c > @@ -76,7 +76,7 @@ static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata, > } else if ((offset & GENMASK(11, 4)) == TRCSEQEVRn(0)) { > /* sequencer state control registers */ > idx = (offset & GENMASK(3, 0)) / 4; > - if (idx < ETM_MAX_SEQ_STATES) { > + if (idx < ETM_MAX_SEQ_TRANSITIONS) { > reg_csdev->driver_regval = &drvcfg->seq_ctrl[idx]; > err = 0; > } > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h > index 89d81ce4e04e..60e08ab085c5 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.h > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h > @@ -614,6 +614,7 @@ static inline u32 etm4_res_sel_pair(u8 res_sel_idx) > #define ETM_MAX_NR_PE 8 > #define ETMv4_MAX_CNTR 4 > #define ETM_MAX_SEQ_STATES 4 > +#define ETM_MAX_SEQ_TRANSITIONS (ETM_MAX_SEQ_STATES - 1) Similar to the other comment on the patch, please don't tie this to SEQ_STATES. Simpl define. #define ETM_MAX_SEQ_CTRLS 3 Suzuki > #define ETM_MAX_EXT_INP_SEL 4 > #define ETM_MAX_EXT_INP 256 > #define ETM_MAX_EXT_OUT 4 > @@ -877,7 +878,7 @@ struct etmv4_config { > u32 vipcssctlr; > u8 seq_idx; > u8 syncfreq; > - u32 seq_ctrl[ETM_MAX_SEQ_STATES]; > + u32 seq_ctrl[ETM_MAX_SEQ_TRANSITIONS]; > u32 seq_rst; > u32 seq_state; > u8 cntr_idx; > @@ -928,7 +929,7 @@ struct etmv4_save_state { > u32 trcvissctlr; > u32 trcvipcssctlr; > > - u32 trcseqevr[ETM_MAX_SEQ_STATES]; > + u32 trcseqevr[ETM_MAX_SEQ_TRANSITIONS]; > u32 trcseqrstevr; > u32 trcseqstr; > u32 trcextinselr;