From: "Visweswara Tanuku (QUIC)" <quic_vtanuku@quicinc.com>
To: "Visweswara Tanuku (QUIC)" <quic_vtanuku@quicinc.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Cc: "Vijaya Krishna Nivarthi (Temp) (QUIC)"
<quic_vnivarth@quicinc.com>,
"Visweswara Tanuku (QUIC)" <quic_vtanuku@quicinc.com>,
"Mukesh Savaliya (QUIC)" <quic_msavaliy@quicinc.com>
Subject: RE: [PATCH] soc: qcom-geni-se: Update Tx and Rx fifo depth based on QUP HW version
Date: Thu, 8 Dec 2022 04:35:39 +0000 [thread overview]
Message-ID: <31c4f532ec6646f7977ebf930b8a2812@quicinc.com> (raw)
In-Reply-To: <20221121123758.5052-1-quic_vtanuku@quicinc.com>
Gentle Reminder!
-----Original Message-----
From: Visweswara Tanuku <quic_vtanuku@quicinc.com>
Sent: Monday, November 21, 2022 6:08 PM
To: linux-kernel@vger.kernel.org
Cc: Vijaya Krishna Nivarthi (Temp) (QUIC) <quic_vnivarth@quicinc.com>; Visweswara Tanuku (QUIC) <quic_vtanuku@quicinc.com>
Subject: [PATCH] soc: qcom-geni-se: Update Tx and Rx fifo depth based on QUP HW version
From QUP HW Version 3.10 and above the Tx and Rx fifo depth bits are increased to 23:16 bits from
21:16 bits in SE_HW_PARAM registers accomodating 256bytes of fifo depth.
Updated geni_se_get_tx_fifo_depth and
geni_se_get_rx_fifo_depth to retrieve right fifo depth based on QUP HW version.
Signed-off-by: Visweswara Tanuku <quic_vtanuku@quicinc.com>
---
include/linux/qcom-geni-se.h | 42 ++++++++++++++++++++++++++++++------
1 file changed, 36 insertions(+), 6 deletions(-)
diff --git a/include/linux/qcom-geni-se.h b/include/linux/qcom-geni-se.h index f5672785c0c4..5ea5351f8818 100644
--- a/include/linux/qcom-geni-se.h
+++ b/include/linux/qcom-geni-se.h
@@ -242,12 +242,22 @@ struct geni_se {
/* SE_HW_PARAM_0 fields */
#define TX_FIFO_WIDTH_MSK GENMASK(29, 24)
#define TX_FIFO_WIDTH_SHFT 24
+/*
+ * For QUP HW Version >= 3.10 Tx fifo depth support is increased
+ * to 256bytes and corresponding bits are 16 to 23 */
+#define TX_FIFO_DEPTH_MSK_256_BYTES GENMASK(23, 16)
#define TX_FIFO_DEPTH_MSK GENMASK(21, 16)
#define TX_FIFO_DEPTH_SHFT 16
/* SE_HW_PARAM_1 fields */
#define RX_FIFO_WIDTH_MSK GENMASK(29, 24)
#define RX_FIFO_WIDTH_SHFT 24
+/*
+ * For QUP HW Version >= 3.10 Rx fifo depth support is increased
+ * to 256bytes and corresponding bits are 16 to 23 */
+#define RX_FIFO_DEPTH_MSK_256_BYTES GENMASK(23, 16)
#define RX_FIFO_DEPTH_MSK GENMASK(21, 16)
#define RX_FIFO_DEPTH_SHFT 16
@@ -388,7 +398,8 @@ static inline void geni_se_abort_s_cmd(struct geni_se *se)
/**
* geni_se_get_tx_fifo_depth() - Get the TX fifo depth of the serial engine
- * @se: Pointer to the concerned serial engine.
+ * based on QUP HW version
+ * @se: Pointer to the concerned serial engine.
*
* This function is used to get the depth i.e. number of elements in the
* TX fifo of the serial engine.
@@ -397,11 +408,20 @@ static inline void geni_se_abort_s_cmd(struct geni_se *se)
*/
static inline u32 geni_se_get_tx_fifo_depth(struct geni_se *se) {
- u32 val;
+ u32 val, hw_version, hw_major, hw_minor, tx_fifo_depth_mask;
+
+ hw_version = geni_se_get_qup_hw_version(se);
+ hw_major = GENI_SE_VERSION_MAJOR(hw_version);
+ hw_minor = GENI_SE_VERSION_MINOR(hw_version);
+
+ if ((hw_major == 3 && hw_minor >= 10) || hw_major > 3)
+ tx_fifo_depth_mask = TX_FIFO_DEPTH_MSK_256_BYTES;
+ else
+ tx_fifo_depth_mask = TX_FIFO_DEPTH_MSK;
val = readl_relaxed(se->base + SE_HW_PARAM_0);
- return (val & TX_FIFO_DEPTH_MSK) >> TX_FIFO_DEPTH_SHFT;
+ return (val & tx_fifo_depth_mask) >> TX_FIFO_DEPTH_SHFT;
}
/**
@@ -424,7 +444,8 @@ static inline u32 geni_se_get_tx_fifo_width(struct geni_se *se)
/**
* geni_se_get_rx_fifo_depth() - Get the RX fifo depth of the serial engine
- * @se: Pointer to the concerned serial engine.
+ * based on QUP HW version
+ * @se: Pointer to the concerned serial engine.
*
* This function is used to get the depth i.e. number of elements in the
* RX fifo of the serial engine.
@@ -433,11 +454,20 @@ static inline u32 geni_se_get_tx_fifo_width(struct geni_se *se)
*/
static inline u32 geni_se_get_rx_fifo_depth(struct geni_se *se) {
- u32 val;
+ u32 val, hw_version, hw_major, hw_minor, rx_fifo_depth_mask;
+
+ hw_version = geni_se_get_qup_hw_version(se);
+ hw_major = GENI_SE_VERSION_MAJOR(hw_version);
+ hw_minor = GENI_SE_VERSION_MINOR(hw_version);
+
+ if ((hw_major == 3 && hw_minor >= 10) || hw_major > 3)
+ rx_fifo_depth_mask = RX_FIFO_DEPTH_MSK_256_BYTES;
+ else
+ rx_fifo_depth_mask = RX_FIFO_DEPTH_MSK;
val = readl_relaxed(se->base + SE_HW_PARAM_1);
- return (val & RX_FIFO_DEPTH_MSK) >> RX_FIFO_DEPTH_SHFT;
+ return (val & rx_fifo_depth_mask) >> RX_FIFO_DEPTH_SHFT;
}
void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr);
--
2.17.1
next prev parent reply other threads:[~2022-12-08 4:35 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-21 12:37 Visweswara Tanuku
2022-12-08 4:35 ` Visweswara Tanuku (QUIC) [this message]
2023-01-05 8:04 ` Visweswara Tanuku (QUIC)
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