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([2a02:810d:15c0:828:f9e3:1d38:66a7:ae92]) by smtp.gmail.com with ESMTPSA id h20-20020a1709067cd400b0094a86ccb634sm5278610ejp.210.2023.04.16.10.29.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 16 Apr 2023 10:29:33 -0700 (PDT) Message-ID: <31c582a7-682a-330e-51d4-53b4a0c5f3a2@linaro.org> Date: Sun, 16 Apr 2023 19:29:32 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH v4 1/3] dt-bindings: phy: Add starfive,jh7110-dphy-rx Content-Language: en-US To: Changhuang Liang , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel Cc: Jack Zhu , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org References: <20230412084540.295411-1-changhuang.liang@starfivetech.com> <20230412084540.295411-2-changhuang.liang@starfivetech.com> <8dd0dc63-e0df-8764-f756-da032d9d671c@linaro.org> <0c94aadf-fac3-d05c-1c54-ae8337526849@starfivetech.com> From: Krzysztof Kozlowski In-Reply-To: <0c94aadf-fac3-d05c-1c54-ae8337526849@starfivetech.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 13/04/2023 11:02, Changhuang Liang wrote: > > > On 2023/4/13 16:41, Krzysztof Kozlowski wrote: >> On 13/04/2023 04:34, Changhuang Liang wrote: >>>>>>> + lane_maps: >>>>>> >>>>>> Why did this appear? Underscores are not allowed. It looks like you >>>>>> re-implement some standard property. >>>>>> >>>>> >>>>> Will change to lane-maps. >>>>> Yes, according to Vinod advice, lane mapping table use device tree >>>>> to parse makes sense. >>>> >>>> Hm, I have a feeling that I saw such property, so you should dig into >>>> existing and in-flight bindings. >>>> >>>> Best regards, >>>> Krzysztof >>>> >>> >>> A standard property? Like "clocks" or "resets"? >> >> Like lane-polarities now submitted to one MIPI. >> >> Anyway it does not look like a property of a board. You said it is fixed >> per SoC, so it should be implied from the compatible. Otherwise please >> explain in description and provide some rationale. >> >> Best regards, >> Krzysztof >> > > This property is the only one used for this IP, I have compared this IP with > other DPHY rx module, DPHY modules form the other manufacturers not have this > configure. > And we also have a SoC called JH7100. It DPHY rx module is the same as JH7110. > But we don't do the upstream work on it. If it use this lane-maps will be > configure as "lane_maps = /bits/ 8 <0 1 2 3 4 5>;". And JH7100 is different SoC, so you have different compatible. Again - is this board specific? If not, looks like SoC specific, thus imply it from compatible. Best regards, Krzysztof