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From: Marek Vasut <marek.vasut@gmail.com>
To: Boris Brezillon <boris.brezillon@bootlin.com>
Cc: masonccyang@mxic.com.tw, broonie@kernel.org,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	Simon Horman <horms@verge.net.au>,
	juliensu@mxic.com.tw, linux-kernel@vger.kernel.org,
	linux-renesas-soc@vger.kernel.org, linux-spi@vger.kernel.org,
	tpiepho@impinj.com, zhengxunli@mxic.com.tw
Subject: Re: [PATCH 1/2] spi: Add Renesas R-Car RPC SPI controller driver
Date: Tue, 20 Nov 2018 14:35:30 +0100	[thread overview]
Message-ID: <31c9518a-2088-7c3f-aec0-9e1b69b30745@gmail.com> (raw)
In-Reply-To: <20181120143209.49217efb@bbrezillon>

On 11/20/2018 02:32 PM, Boris Brezillon wrote:
> On Tue, 20 Nov 2018 14:09:05 +0100
> Marek Vasut <marek.vasut@gmail.com> wrote:
> 
>> On 11/20/2018 08:23 AM, masonccyang@mxic.com.tw wrote:
>>> Hi Marek,  
>>
>> Hi,
>>
>>>> Marek Vasut <marek.vasut@gmail.com>
>>>> 2018/11/19 下午 10:12
>>>>
>>>> To
>>>>  
>>>>> +
>>>>> +static int rpc_spi_set_freq(struct rpc_spi *rpc, unsigned long freq)
>>>>> +{
>>>>> +   int ret;
>>>>> +
>>>>> +   if (rpc->cur_speed_hz == freq)
>>>>> +      return 0;
>>>>> +
>>>>> +   clk_disable_unprepare(rpc->clk_rpc);
>>>>> +   ret = clk_set_rate(rpc->clk_rpc, freq);
>>>>> +   if (ret)
>>>>> +      return ret;
>>>>> +
>>>>> +   ret = clk_prepare_enable(rpc->clk_rpc);
>>>>> +   if (ret)
>>>>> +      return ret;  
>>>>
>>>> Is this clock disable/update/enable really needed ? I'd think that
>>>> clk_set_rate() would handle the rate update correctly.  
>>>
>>> This is for run time PM mechanism in spi-mem layer and __spi_sync(),
>>> you may refer to another patch [1].
>>>
>>> [1]
>>> https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git/commit/?h=for-4.21&id=b942d80b0a394e8ea18fce3b032b4700439e8ca3  
>>
>> I think Geert commented on the clock topic, so let's move it there.
>> Disabling and enabling clock to change their rate looks real odd to me.
> 
> Look at the CLK_SET_RATE_GATE definition and its users and you'll see
> it's not unusual to have such constraints on clks. Maybe your HW does
> not have such constraints, but it's not particularly odd to do that
> (though it could probably be automated by the clk framework somehow).

I think you stated my concern right at the end, good, no need for me to
add to this. Yes, I don't think any random driver should deal with
peculiarities of the clock controller.

-- 
Best regards,
Marek Vasut

  reply	other threads:[~2018-11-20 13:35 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-19 10:01 [PATCH 0/2] spi: Add Renesas R-Car D3 RPC SPI driver Mason Yang
2018-11-19 10:01 ` [PATCH 1/2] spi: Add Renesas R-Car RPC SPI controller driver Mason Yang
2018-11-19 14:12   ` Marek Vasut
2018-11-19 15:27     ` Mark Brown
2018-11-19 22:10       ` Marek Vasut
2018-11-20 13:26         ` Mark Brown
2018-11-20 13:33           ` Marek Vasut
     [not found]     ` <OF4FAD10C5.F4F6D29B-ON4825834B.001FAB40-4825834B.00289635@mxic.com.tw>
2018-11-20 13:09       ` Marek Vasut
2018-11-20 13:32         ` Boris Brezillon
2018-11-20 13:35           ` Marek Vasut [this message]
     [not found]     ` <OF5B1A3AE4.2DEECF37-ON4825834E.00031E97-4825834E.00042D72@mxic.com.tw>
2018-11-23 13:34       ` Marek Vasut
2018-11-20  2:04   ` kbuild test robot
2018-11-20  5:49   ` kbuild test robot
2018-11-20  8:01   ` Geert Uytterhoeven
2018-11-20  8:10     ` Boris Brezillon
2018-11-19 10:01 ` [PATCH 2/2] dt-binding: spi: Document Renesas R-Car RPC controller bindings Mason Yang
2018-11-19 13:49   ` Marek Vasut
2018-11-19 14:10     ` Boris Brezillon
2018-11-19 14:14       ` Marek Vasut
2018-11-19 14:43         ` Boris Brezillon
2018-11-19 15:12           ` Marek Vasut
2018-11-19 15:21             ` Boris Brezillon
2018-11-19 22:11               ` Marek Vasut
2018-11-19 22:19                 ` Boris Brezillon
2018-11-19 22:22                   ` Marek Vasut
2018-11-19 22:25                     ` Boris Brezillon
2018-11-19 22:29                       ` Marek Vasut
2018-11-19 22:31                         ` Boris Brezillon
     [not found]     ` <OFDD04CD59.10199EDD-ON4825834B.001E1390-4825834B.001F65DD@mxic.com.tw>
2018-11-20 12:57       ` Marek Vasut
     [not found]         ` <OF26D8352D.B4B02BBE-ON4825834C.00043726-4825834C.0004E2F7@mxic.com.tw>
2018-11-21  1:51           ` Marek Vasut
2018-11-20  8:07   ` Geert Uytterhoeven
2018-11-20 13:56   ` kbuild test robot

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