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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjA1MDA3NiBTYWx0ZWRfX3xbNI9dGeqny boDU3jtW2luD7yipJK8Z7O+mm3YlH5ON8HMkJYg7WIiGLiBillhWIpypG7G3ZHemx4XdpIjMEaX VUJGqSOBPd2MH6rQEbZB8dSvS55mqcnmlgconFH26m16CXG+YrI8vBRLV+USIemYctxeUwtfB39 RAOQhWTrUbo8KIJmPLrFO+HW8qCnhm00BNSQjmUlSbrpXoDbB+WRryDvHHyaZ22ihBNfCbxS6P8 BykzHcUIbzBxbeP28k7U7IqhNZ435XXALeItwHF2gvVezXIJZT6Dn7Dwsehnzzp6nGC2b/nGnkI SFLaMpfmHDOtvbiAEgEaxmqWLGMSCs2e8rclLwMt7KrYZnr51LilOWyI0T5NRoVwZCiOnmbbk7O uduxJdRVtnla3XHGze9qHTPfzNOuMQ== X-Proofpoint-ORIG-GUID: hPjMOvO2UTAQ2nWsfFpJJDrPacTEjpHC X-Authority-Analysis: v=2.4 cv=DplbOW/+ c=1 sm=1 tr=0 ts=6932b3c8 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=v+kbWGyw1T97G6+vs1uYIQ==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=QEzaw7COleC6pDHmt4MA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: hPjMOvO2UTAQ2nWsfFpJJDrPacTEjpHC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-05_03,2025-12-04_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 bulkscore=0 spamscore=0 adultscore=0 malwarescore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512050076 Hi Konrad, On 12/4/2025 7:14 PM, Konrad Dybcio wrote: > On 11/27/25 10:43 AM, Harshal Dev wrote: >> On X Elite, there is a crypto engine IP block similar to ones found on >> SM8x50 platforms. >> >> Describe the crypto engine and its BAM. >> >> Signed-off-by: Harshal Dev >> --- >> The dt-binding schema update for the x1e80100 compatible is here >> (already merged): >> >> https://lore.kernel.org/all/20250213-dt-bindings-qcom-qce-x1e80100-v1-1-d17ef73a1c12@linaro.org/ >> --- >> Changes in v3: >> - Fixed num-channels and qcom,num-ees properties by updating them to 20 and 4 respectively. >> - Link to v2: https://lore.kernel.org/all/20250221-x1e80100-crypto-v2-1-413ecf68dcd7@linaro.org >> Changes in v2: >> - Added EE and channels numbers in BAM node, like Stephan suggested. >> - Added v1.7.4 compatible as well. >> - Link to v1: https://lore.kernel.org/r/20250213-x1e80100-crypto-v1-1-f93afdd4025a@linaro.org >> --- >> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 24 ++++++++++++++++++++++++ >> 1 file changed, 24 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi >> index 51576d9c935d..a1cadcce98e1 100644 >> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi >> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi >> @@ -3033,6 +3033,30 @@ usb_1_ss2_qmpphy_dp_in: endpoint { >> }; >> }; >> >> + cryptobam: dma-controller@1dc4000 { >> + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; >> + reg = <0x0 0x01dc4000 0x0 0x28000>; >> + interrupts = ; >> + #dma-cells = <1>; >> + iommus = <&apps_smmu 0x480 0x0000>, >> + <&apps_smmu 0x481 0x0000>; > > Just 0x0 is good Acknowledge. > >> + qcom,ee = <0>; >> + qcom,controlled-remotely; >> + num-channels = <20>; >> + qcom,num-ees = <4>; >> + }; >> + >> + crypto: crypto@1dfa000 { >> + compatible = "qcom,x1e80100-qce", "qcom,sm8150-qce", "qcom,qce"; >> + reg = <0x0 0x01dfa000 0x0 0x6000>; >> + dmas = <&cryptobam 4>, <&cryptobam 5>; >> + dma-names = "rx", "tx"; > > one a line, please I did not quite get this comment, could you please clarify a bit more? :) > >> + iommus = <&apps_smmu 0x480 0x0000>, >> + <&apps_smmu 0x481 0x0000>; >> + interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; > > 0 -> QCOM_ICC_TAG_ALWAYS Acknowledge. Regards, Harshal > > Konrad