From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C15B28BA95; Sat, 7 Mar 2026 17:00:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772902836; cv=none; b=XRQYma7XKt67zv4tSMLIpMykLvhsmBBFNj0l5x/Z+2QtdEcdc7PMAID9bejBhL1EJ3rmhGRaBxh1WACJxIiXvE0aBGnRi6yS8I+VJgjprPxo+WGyPOkp/1Cv3b/bjuS7KyWIZUaAYmGJ/RgKXvsZTYG3JhdtmRAS/hDFYVjoHlA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772902836; c=relaxed/simple; bh=QzyIgUj4+TZNvHFeeSTMTUDfTst/iado3kuR01j9w0Y=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=RhihaMaMoi5gARHZCMEoz5RSfSpG47l5CVpsVYg0HIGZNaTHUmDNCDFO4L4BILj00L89E25Rc0veeaTqKMVErj13XRMPlwUFvRiGXMaeKKvZ4fM9UhY0K3vUKIUAxk+/YdH7GxT83O6wBAB1+ECHOli1UazcTl0PcGqVA0A5Uas= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qcwMt/do; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qcwMt/do" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8CFC0C19422; Sat, 7 Mar 2026 17:00:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772902835; bh=QzyIgUj4+TZNvHFeeSTMTUDfTst/iado3kuR01j9w0Y=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=qcwMt/doscMRJ/OBMXSMuZzh5/ozJraGofdgn1VFs3RIGTDdJJaikoknU8sQ7ffCv qRpIrOhPWWTpxfoy9cmKRoajUgn3TawTJYV2ULjJDsaf8/KUURLIdB94PhQ9Oq3cAw ce95lM/gKJqTYWmWEFKMuyLWS/QoG7M8eH7KbH5bLhOJgHKf4YqnZdb/Qut13NNUop iHptRb9XHS/BpE7JVgF4FwENj2J7xWaSKuFw/sWGu563/PEiDYg8kqL5KPPe9jdOaf ZOqqcETEgQLEIQY7tdQxvL3d0szyuJ0bFObmk7p/DvmmHq6jY6tBECUGpDSc16I1p0 ASAgbWyqp2UJQ== Message-ID: <31fff84b-30d2-430e-8794-47b4ee7d5317@kernel.org> Date: Sat, 7 Mar 2026 18:00:33 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 0/6] memory: tegra: Add MC error logging support for Tegra264 SoC To: Ketan Patil , thierry.reding@gmail.com, jonathanh@nvidia.com Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org References: <20260226163115.1152181-1-ketanp@nvidia.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 26/02/2026 17:31, Ketan Patil wrote: > In Tegra264, different components from memory subsystems like Memory > Controller Fabric (MCF), HUB, HUB Common (HUBC), Side Band Shim (SBS) > and MC Channels have different interrupt lines for receiving memory > controller error interrupts. This patch set includes changes to add > support and enable Memory Controller error logging for Tegra264. > > Ketan Patil (6): > memory: tegra: Group error handling related registers > memory: tegra: Group register and fields > memory: tegra: Add support for multiple IRQs > memory: tegra: Group SoC specific fields > memory: tegra: Prepare for supporting multiple intmask registers > memory: tegra: Add MC error logging support for Tegra264 > Please use checkpatch. You should run it, not the maintainer. CHECK: Alignment should match open parenthesis CHECK: Please don't use multiple blank lines Best regards, Krzysztof