From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752531AbbIDDGf (ORCPT ); Thu, 3 Sep 2015 23:06:35 -0400 Received: from mailout4.samsung.com ([203.254.224.34]:49177 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751092AbbIDDGd (ORCPT ); Thu, 3 Sep 2015 23:06:33 -0400 X-AuditID: cbfee68d-f79106d00000728c-64-55e90ab65c06 Date: Fri, 04 Sep 2015 03:06:30 +0000 (GMT) From: Sarbojit Ganguly Subject: [PATCH v2] arm: Adding support for atomic half word exchange To: Sarbojit Ganguly , "linux@arm.linux.org.uk" , Will Deacon Cc: Catalin Marinas , "linux-arm-kernel@lists.infradead.org" , SHARAN ALLUR , VIKRAM MUPPARTHI , "peterz@infradead.org" , "Waiman.Long@hp.com" , "linux-kernel@vger.kernel.org" , "torvalds@linux-foundation.org" , SUNEEL KUMAR SURIMANI Reply-to: ganguly.s@samsung.com MIME-version: 1.0 X-MTR: 20150904025757044@ganguly.s Msgkey: 20150904025757044@ganguly.s X-EPLocale: en_US.windows-1252 X-Priority: 3 X-EPWebmail-Msg-Type: personal X-EPWebmail-Reply-Demand: 0 X-EPApproval-Locale: X-EPHeader: ML X-MLAttribute: X-RootMTR: 20150820142334293@ganguly.s X-ParentMTR: 20150820142334293@ganguly.s X-ArchiveUser: X-CPGSPASS: Y X-ConfirmMail: N,general Content-type: text/plain; charset=windows-1252 MIME-version: 1.0 Message-id: <320411514.5779181441335987727.JavaMail.weblogic@ep2mlwas01a> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrGIsWRmVeSWpSXmKPExsWyRsSkWncb18tQgwX3rCwu75rD5sDo8XmT XABjFJdNSmpOZllqkb5dAlfG1LXrWAp6TCtWHDzC1sB4w7iLkYNDSEBFom9SRBcjJ4eEgInE sg2zmSFsMYkL99azdTFyAZUsZZT4f+A4C0g9SNGO9dkQ8TmMEl17O5lAGliA5ry6dRismU1A X+L0/pdgcWEBV4nGP4tZQRpEBLoYJU4ueMIO4jALvGGW+LT/CyNIlZCAvET7i+1gHbwCghIn Zz5hgThDSWL1n4XMEHFliW873kKdJyexZOplJgibV2JG+1MWmPi0r2ugaqQlzs/awAjzzuLv j6Hi/BLHbu+A6hWQmHrmIFSNusTSf9+gbE2Jo69+w9XvOrWcGWZXw8bf7BC2hMTWliesIDaz gKLElO6H7BC2gcSRRXNY0f3CK+Ap8fzrdrDnJQSmckicutLEPIFRaRaSullIZs1CMgtZzQJG llWMoqkFyQXFSelFhnrFibnFpXnpesn5uZsYgcnh9L9nvTsYbx+wPsQowMGoxMN74seLUCHW xLLiytxDjKbAmJrILCWanA9MQXkl8YbGZkYWpiamxkbmlmZK4ryKUj+DhQTSE0tSs1NTC1KL 4otKc1KLDzEycXBKNTCGPH1n5rrImit+X49DfrWx0PEp8S11HnJObFd/VC7ueZq16VpD1EKx x3+f8Pkrh2399qZstY5oddivCgVHHsN9ArWnTiuvy48P/XvY9F7XFJ7/XzZm3kpa9eW5cGb3 MvM99j9zXiWzzs3YbrWmTHiNhunt0hlCX21WPs5fdmpeLsPSiJfvpD8psRRnJBpqMRcVJwIA IEdqqQkDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrOKsWRmVeSWpSXmKPExsVy+t/tft1tXC9DDS43m1hc3jWHzYHR4/Mm uQDGqDSbjNTElNQihdS85PyUzLx0WyXv4HjneFMzA0NdQ0sLcyWFvMTcVFslF58AXbfMHKCh SgpliTmlQKGAxOJiJX07m6L80pJUhYz84hJbpWhDcyM9IwM9UyM9Q9NYK0MDAyNToJqEtIyp a9exFPSYVqw4eIStgfGGcRcjB4eQgIpE36QIEFNCwERix/rsLkZOIFNM4sK99WxdjFxAFXMY Jbr2djKBJFiAyl/dOswMYrMJ6Euc3v8SLC4s4CrR+GcxK0iDiEAXo8TJBU/YQRxmgTfMEp/2 f2EEqRISkJdof7EdrINXQFDi5MwnLBDrlCRW/1nIDBFXlvi24y0zRFxOYsnUy0wQNq/EjPan LDDxaV/XQNVIS5yftYER5uzF3x9Dxfkljt3eAdUrIDH1zEGoGnWJpf++QdmaEkdf/Yar33Vq OTPMroaNv9khbAmJrS1PWEFsZgFFiSndD9khbAOJI4vmsKL7hVfAU+L51+3sExhlZyFJzULS PgtJO7KaBYwsqxhFUwuSC4qT0iuM9YoTc4tL89L1kvNzNzGCE9GzxTsY/5+3PsQowMGoxMN7 4seLUCHWxLLiytxDjBIczEoivHu/AYV4UxIrq1KL8uOLSnNSiw8xmgLjbSKzlGhyPjBJ5pXE GxqbmJsam1oYGJqbmymJ86qufBYqJJCeWJKanZpakFoE08fEwSnVwBj8V/9m/KxYTsfbwn4v 1s53Urry3sxdJf2989vubZ828rGsczjWm3D32HL+CWbRtSfmf96afP32Waa/i92iq778ZJf9 P1/msulW1fmiomZPogoF5rr4LuA9vLxjwv66oxvMij9u5BYSrL76gOnYkvU+AVKR9bvXfeub oMW/3WftHZ87vNnZlsuVWIozEg21mIuKEwHABKgsWgMAAA== DLP-Filter: Pass X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id t84374kn003486 Hello, This is the second version of the patch previously posted. v1-->v2 : Extended the guard code to cover the byte exchange case as well following opinion of Will Deacon. Checkpatch has been run and issues were taken care of. From: Sarbojit Ganguly Date: Thu, 3 Sep 2015 13:00:27 +0530 Subject: [PATCHv2] ARM: Add support for half-word atomic exchange Since support for half-word atomic exchange was not there and Qspinlock on ARM requires it, modified __xchg() to add support for that as well. ARMv6 and lower does not support ldrex{b,h} so, added a guard code to prevent build breaks. Signed-off-by: Sarbojit Ganguly --- arch/arm/include/asm/cmpxchg.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h index 916a274..a53cbeb 100644 --- a/arch/arm/include/asm/cmpxchg.h +++ b/arch/arm/include/asm/cmpxchg.h @@ -39,6 +39,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size switch (size) { #if __LINUX_ARM_ARCH__ >= 6 +#if !defined(CONFIG_CPU_V6) case 1: asm volatile("@ __xchg1\n" "1: ldrexb %0, [%3]\n" @@ -49,6 +50,22 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size : "r" (x), "r" (ptr) : "memory", "cc"); break; + + /* + * Half-word atomic exchange, required + * for Qspinlock support on ARM. + */ + case 2: + asm volatile("@ __xchg2\n" + "1: ldrexh %0, [%3]\n" + " strexh %1, %2, [%3]\n" + " teq %1, #0\n" + " bne 1b" + : "=&r" (ret), "=&r" (tmp) + : "r" (x), "r" (ptr) + : "memory", "cc"); + break; +#endif case 4: asm volatile("@ __xchg4\n" "1: ldrex %0, [%3]\n" -- Regards, Sarbojit ------- Original Message ------- Sender : Sarbojit Ganguly Technical Lead/SRI-Bangalore-AP Systems 1/Samsung Electronics Date : Aug 20, 2015 19:55 (GMT+05:30) Title : Re: Re: Re: [PATCH] arm: Adding support for atomic half word exchange >> My apologies, the e-mail editor was not configured properly. >> CC'ed to relevant maintainers and reposting once again with proper formatting. >> >> Since 16 bit half word exchange was not there and MCS based qspinlock >> by Waiman's xchg_tail() requires an atomic exchange on a half word, >> here is a small modification to __xchg() code to support the exchange. >> ARMv6 and lower does not have support for LDREXH, so we need to make >> sure things do not break when we're compiling on ARMv6. >> >> Signed-off-by: Sarbojit Ganguly > >> --- >> arch/arm/include/asm/cmpxchg.h | 18 ++++++++++++++++++ >> 1 file changed, 18 insertions(+) >> >> diff --git a/arch/arm/include/asm/cmpxchg.h >> b/arch/arm/include/asm/cmpxchg.h index 1692a05..547101d 100644 >> --- a/arch/arm/include/asm/cmpxchg.h >> +++ b/arch/arm/include/asm/cmpxchg.h >> @@ -50,6 +50,24 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size >> : "r" (x), "r" (ptr) >> : "memory", "cc"); >> break; >> +#if !defined (CONFIG_CPU_V6) >> + /* >> + * Halfword exclusive exchange >> + * This is new implementation as qspinlock >> + * wants 16 bit atomic CAS. >> + * This is not supported on ARMv6. >> + */ >I don't think you need this comment. We don't use qspinlock on arch/arm/. Yes, till date mainline ARM does not support but I've ported Qspinlock on ARM hence I think that comment might be required. >> + case 2: >> + asm volatile("@ __xchg2 " >> + "1: ldrexh %0, [%3] " >> + " strexh %1, %2, [%3] " >> + " teq %1, #0 " >> + " bne 1b" >> + : "=&r" (ret), "=&r" (tmp) >> + : "r" (x), "r" (ptr) >> + : "memory", "cc"); >> + break; >> +#endif >> case 4: >> asm volatile("@ __xchg4 " >> "1: ldrex %0, [%3] " >We have the same issue with the byte exclusives, so I think you need to extend the guard you're adding to cover that case too (which is a bug in current mainline). Ok, I will work on this and release a v2 soon. >Will - Sarbojit ????? ??? ?? ?? ?? ----------------------------------------------------------------------+ The Tao lies beyond Yin and Yang. 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