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Mon, 21 Sep 2026 02:14:38 -0700 (PDT) X-Received: by 2002:a05:6a20:7f8a:b0:3bf:6222:2e7e with SMTP id adf61e73a8af0-3dd8c3fd41cmr16576663637.4.1789982077898; Mon, 21 Sep 2026 02:14:37 -0700 (PDT) Received: from [10.151.37.217] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33c342b3c67sm18923840eec.10.2026.09.21.02.14.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 21 Sep 2026 02:14:37 -0700 (PDT) Message-ID: <321460f8-f24a-4e91-be17-50f1639f8e76@oss.qualcomm.com> Date: Mon, 21 Sep 2026 14:44:31 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/4] PCI: qcom: Move PHY init and add PHY reset call to align with HPG To: Qiang Yu , Manivannan Sadhasivam , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Vinod Koul , Neil Armstrong , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org References: <20260915-align_pcie_init_sequence_0916-v1-0-0b2195836f30@oss.qualcomm.com> <20260915-align_pcie_init_sequence_0916-v1-1-0b2195836f30@oss.qualcomm.com> Content-Language: en-US From: Kathiravan Thirumoorthy In-Reply-To: <20260915-align_pcie_init_sequence_0916-v1-1-0b2195836f30@oss.qualcomm.com> Content-Type: text/plain; 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move > that ahead of the reset assert to match the same ordering. Also add or > move the PARF_DEVICE_TYPE write to right after the reset group in each of > those four functions. > > For most platforms phy_init()/phy_exit()/phy_reset() are no-ops against > their phy_ops, so moving the calls around has no effect yet; the PHY's > clocks/reset actually start being driven this way once a later PHY driver > change implements phy_ops::init/phy_ops::exit/phy_ops::reset. > phy-qcom-pcie2.c does implement phy_init()/phy_exit(), but moving the call > site into qcom_pcie_host_init()/qcom_pcie_host_deinit() keeps them at the > same point relative to that platform's own clock/reset programming, so its > init sequence doesn't change either. > > Signed-off-by: Qiang Yu > --- > drivers/pci/controller/dwc/pcie-qcom.c | 165 +++++++++++++++++++++++++-------- > 1 file changed, 126 insertions(+), 39 deletions(-) Verified the PCIe enumeration in IPQ9574 and IPQ5424 and it works fine. So, Tested-by: Kathiravan Thirumoorthy #IPQ9574-RDP433, IPQ5424-RDP466