From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E457214A71; Thu, 9 Jan 2025 07:55:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736409354; cv=none; b=XUkZu97d9XFahscS3L3GPo3NJc4nxfEbTX3ko6q79KPRn50Mu9fDl00suimtB5TYjiF8PAilRe6JNesOUDGMYeFbaohiuBtbKQ+SAedN+/VogkJUb0yCIutKjjgKxnf4J5vG1E2UmeWeG0CZzd3+wfJmG8vXloSLWMjaWFlHu/w= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736409354; c=relaxed/simple; bh=wgcey/kQiN800rSSdv2KSbHhuAIs+1NSfhJe54lJy3o=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=CVrqQF/E+SrEJTtgq21eJvfBn2vHBh7QwqtO1byUfWIe+kxmdOM9es8pz2lR1WG1jmTA0t236UewakY5372c9qCDaVbbQcBh63K+Daz7N/PyKGEYBybcPWH70hu9V9XMqwREjkJIvg//SBZ52XEfwORmmMAM3fewF9fCVPAKqZk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=XQzW38XL; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="XQzW38XL" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 60A02C4CED2; Thu, 9 Jan 2025 07:55:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1736409354; bh=wgcey/kQiN800rSSdv2KSbHhuAIs+1NSfhJe54lJy3o=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=XQzW38XL6YK6Nrzoc7Zi39V5umxnrJN8iJ7yKrkDhddQ0MA9aR9E6l6b3Jc/CKREL 8eNwWkJ0l+0VBlgHBrCt9eYF/4nnZElboJDB76zVodb4TxJkQavtQL4LMmNiSZpksC BDLd+tPs2NhMy6jZ2Jmv0Xulv+LJIpXuPIBe33k+viBke3DnBJurxe5JXZDU4uWBH8 EHjK14oPxl0rnEuw87Ov4zZyEPvmjNmNIsgnSapdrD9E8NxpTunxZt5Dja0mjsuTSj rZj2fXCH+uhpdnoawiFmj5xH6uO16YFqBE+L4DB0fGgED2foQrTBwiSVFXP2Sncb/R jZhmLyVqNROIg== Message-ID: <325c495b-8e5a-412f-9974-3ec7ab15b479@kernel.org> Date: Thu, 9 Jan 2025 08:55:43 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 7/7] arm64: dts: mediatek: add display support for mt8365-evk To: Alexandre Mergnat , Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jitao Shi , CK Hu , Catalin Marinas , Will Deacon , Simona Vetter , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20231023-display-support-v5-0-3905f1e4b835@baylibre.com> <20231023-display-support-v5-7-3905f1e4b835@baylibre.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 08/01/2025 17:15, Alexandre Mergnat wrote: > > +&i2c1 { > + #address-cells = <1>; > + #size-cells = <0>; > + clock-div = <2>; > + clock-frequency = <100000>; > + pinctrl-0 = <&i2c1_pins>; > + pinctrl-names = "default"; > + status = "okay"; > + > + it66121_hdmi: hdmi@4c { > + #sound-dai-cells = <0>; compatible is always, ALWAYS first. > + compatible = "ite,it66121"; reg follows. > + interrupt-parent = <&pio>; > + interrupts = <68 IRQ_TYPE_LEVEL_LOW>; > + pinctrl-0 = <&ite_pins>; > + pinctrl-names = "default"; > + reg = <0x4c>; > + reset-gpios = <&pio 69 GPIO_ACTIVE_LOW>; > + vcn18-supply = <&mt6357_vsim2_reg>; > + vcn33-supply = <&mt6357_vibr_reg>; > + vrf12-supply = <&mt6357_vrf12_reg>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0>; > + it66121_in: endpoint@0 { > + reg = <0>; > + bus-width = <12>; > + remote-endpoint = <&dpi0_out>; > + }; > + }; > + > + port@1 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <1>; > + hdmi_connector_out: endpoint@0 { > + reg = <0>; > + remote-endpoint = <&hdmi_connector_in>; > + }; > + }; > + }; > + }; > +}; > + > &mmc0 { > assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>; > assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>; > @@ -205,6 +362,11 @@ &mt6357_pmic { > mediatek,micbias1-microvolt = <1700000>; > }; > > +&mt6357_vsim1_reg { > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > +}; > + > &pio { > aud_default_pins: audiodefault-pins { > clk-dat-pins { > @@ -267,6 +429,49 @@ clk-dat-pins { > }; > }; > > + dpi_default_pins: dpi-default-pins { > + pins { > + pinmux = , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + drive-strength = <4>; > + }; > + }; > + > + dpi_idle_pins: dpi-idle-pins { > + pins { > + pinmux = , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + }; > + }; > + > ethernet_pins: ethernet-pins { > phy_reset_pins { > pinmux = ; > @@ -308,6 +513,33 @@ pins { > }; > }; > > + i2c1_pins: i2c1-pins { > + pins { > + pinmux = , > + ; > + bias-pull-up; > + }; > + }; > + > + ite_pins: ite-pins { > + irq_ite_pins { That's some downstream copy-paste. Align DTS coding style. Best regards, Krzysztof