From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: ARC-Seal: i=1; a=rsa-sha256; t=1517222722; cv=none; d=google.com; s=arc-20160816; b=LTSAlBMoVlIHJFGnd1kDIvHBvDBlKGHKLMoXLTwp1GsaJQkXqR5BUsKc1ZzfKHxzwl /urACJsirnm7Cu7vRpzfMfWAmTkV2iCY2kpz4tbUt7rEfSMXxbxqzW9p0DF4uJyUIQND KBEnovLYkYfQyDnAJNsGAoDDHPU+9Jox3i99bMN3QIh5x12SJYoE9LXjDWb2sL9f/h+A ZrRmFZWythN6mm9Lykk3oUCE9HKpc35prZ6DAxk9vWyt0ukyA5uQa9EWOSHt9/Pw+8QM UyPve+BDXRLgNfTuwJoA/rX3915j7LZCySVKr5X7WAe6OUqrlkzhbLiFrm83xcmmr8vn /h5g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:content-language:in-reply-to:mime-version :user-agent:date:message-id:from:references:cc:to:subject:sender :dkim-signature:arc-authentication-results; bh=K1hDG1bDE+wyIW057I+OM4Q6vnh3CZc+PCPPJqa/1TI=; b=KKU2qK3uXaoXY5IWy1Hphs4713HB4PvH+tRMJj2/fq/yjw47jqg7eLZfutullH+WrR tesRbPbf9Avs2jwY5EGBlKFszRdV8hcJOQvbgr48ATV3kvit1793MIGUNEQZwnHHsp6T 2rkpvmFHhXgVG7GXNn0wP32Kw2PlUSj3AnrHW3cLJUjs4EJbBHlIBLlRtYspa+pVtQJd Cakobfkuannq1Li3EErsSWcd/Rde3VmUP78SXzJ5Rb0ue26n5LV8j1QB1jchutyTrnHT io3HBtgn9yfKVGxNMGwGH5BFr+KsaemoByYjxe3A+gPQgVHUG3CuPBS+nkAuXDZnpt3P P/fA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=BV1Fxtyy; spf=pass (google.com: domain of paolo.bonzini@gmail.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=paolo.bonzini@gmail.com; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=redhat.com Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=BV1Fxtyy; spf=pass (google.com: domain of paolo.bonzini@gmail.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=paolo.bonzini@gmail.com; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=redhat.com X-Google-Smtp-Source: AH8x225Lrb7sSvMlMeWID0YcyhViGKzK2dQZHR78QGEV7/RNFAa63hC8UC/H9R/S5W6neblf6HE34Q== Sender: Paolo Bonzini Subject: Re: [PATCH v2 4/4] x86: vmx: Allow direct access to MSR_IA32_ARCH_CAPABILITIES To: KarimAllah Ahmed , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, x86@kernel.org Cc: Asit Mallick , Dave Hansen , Arjan Van De Ven , Tim Chen , Linus Torvalds , Andrea Arcangeli , Andi Kleen , Thomas Gleixner , Dan Williams , Jun Nakajima , Andy Lutomirski , Greg KH , Ashok Raj References: <1517187532-32286-1-git-send-email-karahmed@amazon.de> <1517187532-32286-5-git-send-email-karahmed@amazon.de> From: Paolo Bonzini Message-ID: <32627024-026c-4415-8153-bfb9778877b8@redhat.com> Date: Mon, 29 Jan 2018 11:45:22 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.2 MIME-Version: 1.0 In-Reply-To: <1517187532-32286-5-git-send-email-karahmed@amazon.de> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1590886528088148863?= X-GMAIL-MSGID: =?utf-8?q?1590923334032818246?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: On 29/01/2018 01:58, KarimAllah Ahmed wrote: > Add direct access to MSR_IA32_SPEC_CTRL for guests. Future intel processors > will use this MSR to indicate RDCL_NO (bit 0) and IBRS_ALL (bit 1). This has to be customizable per-VM (similar to the patches Amazon posted a while ago for UCODE_REV for example). It's not urgent anyway given that no processor has it yet. Thanks, Paolo > Cc: Asit Mallick > Cc: Dave Hansen > Cc: Arjan Van De Ven > Cc: Tim Chen > Cc: Linus Torvalds > Cc: Andrea Arcangeli > Cc: Andi Kleen > Cc: Thomas Gleixner > Cc: Dan Williams > Cc: Jun Nakajima > Cc: Andy Lutomirski > Cc: Greg KH > Cc: Paolo Bonzini > Cc: Ashok Raj > Signed-off-by: KarimAllah Ahmed > --- > arch/x86/kvm/cpuid.c | 4 +++- > arch/x86/kvm/vmx.c | 2 ++ > 2 files changed, 5 insertions(+), 1 deletion(-) > > diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c > index 32c0c14..2339b1a 100644 > --- a/arch/x86/kvm/cpuid.c > +++ b/arch/x86/kvm/cpuid.c > @@ -71,6 +71,7 @@ u64 kvm_supported_xcr0(void) > #define KVM_CPUID_BIT_AVX512_4VNNIW 2 > #define KVM_CPUID_BIT_AVX512_4FMAPS 3 > #define KVM_CPUID_BIT_IBRS 26 > +#define KVM_CPUID_BIT_ARCH_CAPABILITIES 29 > #define KF(x) bit(KVM_CPUID_BIT_##x) > > int kvm_update_cpuid(struct kvm_vcpu *vcpu) > @@ -394,7 +395,8 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function, > /* cpuid 7.0.edx*/ > const u32 kvm_cpuid_7_0_edx_x86_features = > KF(AVX512_4VNNIW) | KF(AVX512_4FMAPS) | \ > - (boot_cpu_has(X86_FEATURE_IBRS) ? KF(IBRS) : 0); > + (boot_cpu_has(X86_FEATURE_IBRS) ? KF(IBRS) : 0) | \ > + (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES) ? KF(ARCH_CAPABILITIES) : 0); > > /* all calls to cpuid_count() should be made on the same cpu */ > get_cpu(); > diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c > index f82a44c..99cb761 100644 > --- a/arch/x86/kvm/vmx.c > +++ b/arch/x86/kvm/vmx.c > @@ -9617,6 +9617,8 @@ static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id) > > if (boot_cpu_has(X86_FEATURE_IBPB)) > vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_PRED_CMD, MSR_TYPE_RW); > + if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) > + vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_ARCH_CAPABILITIES, MSR_TYPE_R); > vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW); > vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW); > vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW); >