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Fri, 10 Jul 2026 17:52:56 -0700 From: Nicolin Chen To: , , CC: , , , , , , , Subject: [PATCH v8 2/9] iommu/arm-smmu-v3: Skip EVTQ/PRIQ setup in kdump kernel Date: Fri, 10 Jul 2026 17:52:43 -0700 Message-ID: <327616f41b75c5b3d4bb0b4575627b86b6586887.1783729633.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CEB:EE_|SJ2PR12MB8955:EE_ X-MS-Office365-Filtering-Correlation-Id: 6f3c391d-9fef-4ea2-3100-08dedee6c662 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|376014|1800799024|23010399003|82310400026|11063799006|56012099006|6133799003|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: iIZJ4Ms2fAZWgpvBx0DU6yE401Eo8FqM/P2jZ58b2sEUs46G8pA2QCanoASm7bRlKxkEi4zbmcBVYY2F4iyvzfdOS9Z4Ag9TlxcAfCNktD+EXsmspVn63ewUPWtVy8g3fos2LP6/cxOSBG1W/JhZqaV+oDzKYLIaS6bTFxNPVahMlmH/x+bKTbnkkjFg8wzMcj+aIcM2RhubZcriWgzAnKI/oLs6EuME2G4n+lrFzZgdW1XwzdoY93zhaDOZEJCv2slpW/A4HveQO9pujBO5cy88eGHcyoPGXenoOxF7TkN18MT5wBpVKotVICmqIuqYjpxBweyh9mUKl+dYIeffxfPWFIhgbUJOp3Kdp1reXCDlJqXyj5BcH0HeT3VgWVLku4/SR/WO85cmWdkLqFmzh/Y290ceSA3vPKysAJ48rP5v8rGb6bsEEEkMvTjr+KEtLEcqmXtE2yi4fUMJ8TplfWGIb/5JDGxEicp+x6g9Hl7MFap9c87b3XfhhHQls/smAuvaAzH4W2dLeT/NbDP8J5jB4d+hLxjXb41X4C3VEYUd9ki1945jIuqby6rI8UzAV9HMwPTcn2K6V1N3dDw50uiBJMCAgzyQYAHon1oiPN4dXLaL05Wmh3rUanRUybSq48VVSEq1NtNSXBmduqhpipB96cie7GiElbidZfHk5EC4OasT+NGZrFs0Y5i0rixy1uVUDLIbsp8TlmXf86w8oA== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(376014)(1800799024)(23010399003)(82310400026)(11063799006)(56012099006)(6133799003)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: P+K5Qwd8/7Pnw3YEQZbhIJDxTKTidalLsW+Oiv6oDSx0SKwwGl5ne1ItbrMpMyRxp9LsoT1Uy2eGNZzKf/IyST5IoKSKjyBcdHWs7ys8SiO559NuLZYsJMKGKVgl6P3Op2PjJh4NimwvJEYbOMXMVCX3frBi1KVS2/ZDkC/ZBXbYYBgJ1RUo1KaKj6pvJ+I4S2ejTgBKEnpTpk+t7G/VJKgy5VjIK1GiblANOlHNuvy1Z5QHYw4CPzZDd2tAOxCs04JCtEolBtB5YJ1zOCm3gjQYb2Raqkr3vClKzrHwgG/eKZB9nQJmBroAnLea0rMYDy1YZwEpTSSGXIWOpCKr0V6kMJoSUPsWQnHB4SQzZ3zhza1bP3dP9haFtQ/ffFwduDFjqDH5EcryqMVmfbyp47FfsgYfwAX5DkTNt3Jjlu1s7q+ObcMpJdPiTBuwKBWb X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jul 2026 00:53:08.5039 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6f3c391d-9fef-4ea2-3100-08dedee6c662 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CEB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8955 In kdump cases, the crashed kernel's CDs and page tables can be corrupted, which could trigger event spamming. Also, we cannot serve page requests. Skip the EVTQ/PRIQ setup entirely rather than enabling then disabling them. Keep the queue allocations themselves, as their Q_MAX_SZ_SHIFT-capped sizes are negligible against a crashkernel reservation. Also add some inline comments explaining that. Suggested-by: Kevin Tian Reviewed-by: Kevin Tian Reviewed-by: Jason Gunthorpe Reviewed-by: Pranjal Shrivastava Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 44 +++++++++++++-------- 1 file changed, 28 insertions(+), 16 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 404790d2c7210..175964b923716 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -4821,21 +4821,36 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu) arm_smmu_cmdq_issue_cmd_with_sync( smmu, arm_smmu_make_cmd_op(CMDQ_OP_TLBI_NSNH_ALL)); - /* Event queue */ - writeq_relaxed(smmu->evtq.q.q_base, smmu->base + ARM_SMMU_EVTQ_BASE); - writel_relaxed(smmu->evtq.q.llq.prod, smmu->page1 + ARM_SMMU_EVTQ_PROD); - writel_relaxed(smmu->evtq.q.llq.cons, smmu->page1 + ARM_SMMU_EVTQ_CONS); - - enables |= CR0_EVTQEN; - ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, - ARM_SMMU_CR0ACK); - if (ret) { - dev_err(smmu->dev, "failed to enable event queue\n"); - return ret; + /* + * Event queue + * + * Do not enable in a kdump case, as the crashed kernel's CDs and page + * tables might be corrupted, triggering event spamming. A disabled + * queue simply discards new events, without raising any global error. + */ + if (!is_kdump_kernel()) { + writeq_relaxed(smmu->evtq.q.q_base, + smmu->base + ARM_SMMU_EVTQ_BASE); + writel_relaxed(smmu->evtq.q.llq.prod, + smmu->page1 + ARM_SMMU_EVTQ_PROD); + writel_relaxed(smmu->evtq.q.llq.cons, + smmu->page1 + ARM_SMMU_EVTQ_CONS); + + enables |= CR0_EVTQEN; + ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, + ARM_SMMU_CR0ACK); + if (ret) { + dev_err(smmu->dev, "failed to enable event queue\n"); + return ret; + } } - /* PRI queue */ - if (smmu->features & ARM_SMMU_FEAT_PRI) { + /* + * PRI queue + * + * Do not enable in a kdump case, as we cannot serve page requests. + */ + if (!is_kdump_kernel() && (smmu->features & ARM_SMMU_FEAT_PRI)) { writeq_relaxed(smmu->priq.q.q_base, smmu->base + ARM_SMMU_PRIQ_BASE); writel_relaxed(smmu->priq.q.llq.prod, @@ -4868,9 +4883,6 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu) return ret; } - if (is_kdump_kernel()) - enables &= ~(CR0_EVTQEN | CR0_PRIQEN); - /* Enable the SMMU interface */ enables |= CR0_SMMUEN; ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, -- 2.43.0