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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b842a27c0bfsm841928766b.22.2026.01.08.06.10.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 08 Jan 2026 06:10:58 -0800 (PST) Message-ID: <328342d6-e833-4fe7-828f-6978ae17cf0a@oss.qualcomm.com> Date: Thu, 8 Jan 2026 15:10:56 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/5] clk: qcom: cmnpll: Add IPQ5332 SoC support To: Luo Jie , Bjorn Andersson , Michael Turquette , Stephen Boyd , Luo Jie , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_pavir@quicinc.com, quic_suruchia@quicinc.com References: <20260106-qcom_ipq5332_cmnpll-v2-0-f9f7e4efbd79@oss.qualcomm.com> <20260106-qcom_ipq5332_cmnpll-v2-3-f9f7e4efbd79@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260106-qcom_ipq5332_cmnpll-v2-3-f9f7e4efbd79@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=GN8F0+NK c=1 sm=1 tr=0 ts=695fbaf5 cx=c_pps a=KB4UBwrhAZV1kjiGHFQexw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=20ciNqFLEIM2uVeCJLoA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=o1xkdb1NAhiiM49bd1HK:22 X-Proofpoint-GUID: 6j23qTjH36xbI3PamigkrrcI6qe6M0Vp X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTA4MDEwMSBTYWx0ZWRfX5D3D8Q72fhOX MIL9GEsXw5SXKgU24WY/hUKzK0uN99n8k82yGGrqT/HbPJ+eZDtSXsEnl5aeIYHG425tW3f5zur E8rdH0isuCufWVooX4EJZiYn+AiPeMa7od7t1Rfx9LOGfaaPQUpBp65R0IRvZ99lbZlmT40C6Me cIBFWy+hKDT4u8nQUKZkVNlfOZUEp4b8tz+ayiw54bKTWz/IU1Sd9BPXpeG15K2kZXnX4MwnRwn eJzLVwCpaMbNLt5ZZOfxTZFHZTQS3Jh4/cbSMl5IcLfqY5Ni0LiVYdn45mHZRJGFuJ3Gl87Cyt/ Uoc1ueoxWDkdatxr1wNPTrdIp26xpyAfOcTG44gmaGgPdo3iM7VzuGmmcza8uoILewgT+9Uq7pO VADoMFUor1ZVMk9FJV5/JvANGkhkw/KIcb2T2nPOJbIjYRlxIccVp6hJNz7uIMofMXpJ7cZ7ccN Ku4YGkNLAaHU+OIlkew== X-Proofpoint-ORIG-GUID: 6j23qTjH36xbI3PamigkrrcI6qe6M0Vp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-08_03,2026-01-07_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 clxscore=1015 phishscore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 malwarescore=0 impostorscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601080101 On 1/7/26 6:35 AM, Luo Jie wrote: > The CMN PLL in IPQ5332 SoC produces different output clocks when compared > to IPQ9574. While most clock outputs match IPQ9574, the ethernet PHY/switch > (50 Mhz) and PPE clocks (200 Mhz) in IPQ5332 are different. > > Add IPQ5332-specific clock definitions and of_device_id entry. > > Signed-off-by: Luo Jie > --- > drivers/clk/qcom/ipq-cmn-pll.c | 19 ++++++++++++++++++- > 1 file changed, 18 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c > index 369798d1ce42..962462286837 100644 > --- a/drivers/clk/qcom/ipq-cmn-pll.c > +++ b/drivers/clk/qcom/ipq-cmn-pll.c > @@ -1,6 +1,6 @@ > // SPDX-License-Identifier: GPL-2.0-only > /* > - * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. > */ > > /* > @@ -20,6 +20,11 @@ > * and an output clock to NSS (network subsystem) at 300 MHZ. The other output > * clocks from CMN PLL on IPQ5424 are the same as IPQ9574. > * > + * On the IPQ5332 SoC, the CMN PLL provides a single 50 MHZ clock output to > + * the Ethernet PHY (or switch) via the UNIPHY (PCS). It also supplies a 200 > + * MHZ clock to the PPE. The remaining fixed-rate clocks to the GCC and PCS > + * are the same as those in the IPQ9574 SoC. > + * > * +---------+ > * | GCC | > * +--+---+--+ > @@ -51,6 +56,7 @@ > > #include > #include > +#include > #include > > #define CMN_PLL_REFCLK_SRC_SELECTION 0x28 > @@ -117,6 +123,16 @@ static const struct cmn_pll_fixed_output_clk ipq5018_output_clks[] = { > { /* Sentinel */ } > }; > > +static const struct cmn_pll_fixed_output_clk ipq5332_output_clks[] = { > + CLK_PLL_OUTPUT(IPQ5332_XO_24MHZ_CLK, "xo-24mhz", 24000000UL), > + CLK_PLL_OUTPUT(IPQ5332_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), > + CLK_PLL_OUTPUT(IPQ5332_PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL), > + CLK_PLL_OUTPUT(IPQ5332_NSS_300MHZ_CLK, "nss-300mhz", 300000000UL), > + CLK_PLL_OUTPUT(IPQ5332_PPE_200MHZ_CLK, "ppe-200mhz", 200000000UL), > + CLK_PLL_OUTPUT(IPQ5332_ETH_50MHZ_CLK, "eth-50mhz", 50000000UL), > + { /* Sentinel */ } Trusting you on these entries as I can't find a source Reviewed-by: Konrad Dybcio Konrad