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([2a05:6e02:1041:c10:37e6:ed62:3c8b:2621]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-464f5a2850csm42597235e9.19.2025.09.18.07.08.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 18 Sep 2025 07:08:41 -0700 (PDT) Message-ID: <32937382-ad81-4e9b-92d7-798dafea64c1@linaro.org> Date: Thu, 18 Sep 2025 16:08:40 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 2/2] iio: adc: Add the NXP SAR ADC support for the s32g2/3 platforms To: Christophe JAILLET , jic23@kernel.org, dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org, robh@kernel.org, conor+dt@kernel.org, krzk+dt@kernel.org Cc: linux-iio@vger.kernel.org, s32@nxp.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, chester62515@gmail.com, mbrugger@suse.com, ghennadi.procopciuc@oss.nxp.com References: <20250916202605.2152129-1-daniel.lezcano@linaro.org> <20250916202605.2152129-3-daniel.lezcano@linaro.org> Content-Language: en-US From: Daniel Lezcano In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Hi Christophe, On 16/09/2025 22:53, Christophe JAILLET wrote: [ ... ] >> +static int nxp_sar_adc_dma_probe(struct device *dev, struct >> nxp_sar_adc *info) >> +{ >> +    struct device *dev_dma; >> +    u8 *rx_buf; >> + >> +    info->dma_chan = devm_dma_request_chan(dev, "rx"); >> +    if (IS_ERR(info->dma_chan)) >> +        return PTR_ERR(info->dma_chan); >> + >> +    dev_dma = info->dma_chan->device->dev; >> +    rx_buf = dma_alloc_coherent(dev_dma, NXP_SAR_ADC_DMA_BUFF_SZ, >> +                    &info->rx_dma_buf, GFP_KERNEL); > > maybe dmam_alloc_coherent() for the managed version? > This would save some LoC. Ok, thanks for the suggestion, I'll do the change. -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog