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struct rzg3s_pcie_host *host = bus->sysdata; > + > + /* Enable access control to the CFGU */ > + writel_relaxed(RZG3S_PCI_PERM_CFG_HWINIT_EN, > + host->axi + RZG3S_PCI_PERM); > + > + pci_generic_config_write(bus, devfn, where, size, val); why ignore pci_generic_config_write ret ? > + > + /* Disable access control to the CFGU */ > + writel_relaxed(0, host->axi + RZG3S_PCI_PERM); > + > + return PCIBIOS_SUCCESSFUL; > +} > + > +static struct pci_ops rzg3s_pcie_root_ops = { > + .read = pci_generic_config_read, > + .write = rzg3s_pcie_root_write, > + .map_bus = rzg3s_pcie_root_map_bus, > +}; > + > +static void rzg3s_pcie_intx_irq_handler(struct irq_desc *desc) > +{ > + struct rzg3s_pcie_host *host = irq_desc_get_handler_data(desc); > + struct irq_chip *chip = irq_desc_get_chip(desc); > + unsigned int irq = irq_desc_get_irq(desc); > + u32 intx = irq - host->intx_irqs[0]; > + > + chained_irq_enter(chip, desc); > + generic_handle_domain_irq(host->intx_domain, intx); > + chained_irq_exit(chip, desc); > +} > + > +static irqreturn_t rzg3s_pcie_msi_irq(int irq, void *data) > +{ > + u8 regs = RZG3S_PCI_MSI_INT_NR / RZG3S_PCI_MSI_INT_PER_REG; > + DECLARE_BITMAP(bitmap, RZG3S_PCI_MSI_INT_NR); > + struct rzg3s_pcie_host *host = data; > + struct rzg3s_pcie_msi *msi = &host->msi; > + unsigned long bit; > + u32 status; > + > + status = readl_relaxed(host->axi + RZG3S_PCI_PINTRCVIS); > + if (!(status & RZG3S_PCI_PINTRCVIS_MSI)) > + return IRQ_NONE; > + > + /* Clear the MSI */ > + rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIS, > + RZG3S_PCI_PINTRCVIS_MSI, > + RZG3S_PCI_PINTRCVIS_MSI); > + rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_MSGRCVIS, > + RZG3S_PCI_MSGRCVIS_MRI, RZG3S_PCI_MSGRCVIS_MRI); > + > + for (u8 reg_id = 0; reg_id < regs; reg_id++) { > + status = readl_relaxed(host->axi + RZG3S_PCI_MSIRS(reg_id)); > + bitmap_write(bitmap, status, reg_id * RZG3S_PCI_MSI_INT_PER_REG, > + RZG3S_PCI_MSI_INT_PER_REG); > + } > + > + for_each_set_bit(bit, bitmap, RZG3S_PCI_MSI_INT_NR) { > + int ret; > + > + ret = generic_handle_domain_irq(msi->domain, bit); > + if (ret) { > + u8 reg_bit = bit % RZG3S_PCI_MSI_INT_PER_REG; > + u8 reg_id = bit / RZG3S_PCI_MSI_INT_PER_REG; > + > + /* Unknown MSI, just clear it */ > + writel_relaxed(BIT(reg_bit), > + host->axi + RZG3S_PCI_MSIRS(reg_id)); > + } > + } > + > + return IRQ_HANDLED; > +} > + > +static void rzg3s_pcie_msi_irq_ack(struct irq_data *d) > +{ > + struct rzg3s_pcie_msi *msi = irq_data_get_irq_chip_data(d); > + struct rzg3s_pcie_host *host = rzg3s_msi_to_host(msi); > + u8 reg_bit = d->hwirq % RZG3S_PCI_MSI_INT_PER_REG; > + u8 reg_id = d->hwirq / RZG3S_PCI_MSI_INT_PER_REG; > + > + guard(raw_spinlock_irqsave)(&host->hw_lock); > + > + writel_relaxed(BIT(reg_bit), host->axi + RZG3S_PCI_MSIRS(reg_id)); > +} > + > +static void rzg3s_pcie_msi_irq_mask(struct irq_data *d) > +{ > + struct rzg3s_pcie_msi *msi = irq_data_get_irq_chip_data(d); > + struct rzg3s_pcie_host *host = rzg3s_msi_to_host(msi); > + u8 reg_bit = d->hwirq % RZG3S_PCI_MSI_INT_PER_REG; > + u8 reg_id = d->hwirq / RZG3S_PCI_MSI_INT_PER_REG; > + > + guard(raw_spinlock_irqsave)(&host->hw_lock); > + > + rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_MSIRM(reg_id), BIT(reg_bit), > + BIT(reg_bit)); > +} > + > +static void rzg3s_pcie_msi_irq_unmask(struct irq_data *d) > +{ > + struct rzg3s_pcie_msi *msi = irq_data_get_irq_chip_data(d); > + struct rzg3s_pcie_host *host = rzg3s_msi_to_host(msi); > + u8 reg_bit = d->hwirq % RZG3S_PCI_MSI_INT_PER_REG; > + u8 reg_id = d->hwirq / RZG3S_PCI_MSI_INT_PER_REG; > + > + guard(raw_spinlock_irqsave)(&host->hw_lock); > + > + rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_MSIRM(reg_id), BIT(reg_bit), > + 0); > +} > + > +static void rzg3s_pcie_irq_compose_msi_msg(struct irq_data *data, > + struct msi_msg *msg) > +{ > + struct rzg3s_pcie_msi *msi = irq_data_get_irq_chip_data(data); > + struct rzg3s_pcie_host *host = rzg3s_msi_to_host(msi); > + u32 lo, hi; > + > + /* > + * Enable and msg data enable bits are part of the address lo. Drop > + * them along with the unused bit. > + */ > + lo = readl_relaxed(host->axi + RZG3S_PCI_MSIRCVWADRL) & > + RZG3S_PCI_MSIRCVWADRL_MASK; > + hi = readl_relaxed(host->axi + RZG3S_PCI_MSIRCVWADRU); > + > + msg->address_lo = lo; > + msg->address_hi = hi; > + msg->data = data->hwirq; > +} > + > +static struct irq_chip rzg3s_pcie_msi_bottom_chip = { > + .name = "rzg3s-pcie-msi", > + .irq_ack = rzg3s_pcie_msi_irq_ack, > + .irq_mask = rzg3s_pcie_msi_irq_mask, > + .irq_unmask = rzg3s_pcie_msi_irq_unmask, > + .irq_compose_msi_msg = rzg3s_pcie_irq_compose_msi_msg, > +}; > + > +static int rzg3s_pcie_msi_domain_alloc(struct irq_domain *domain, > + unsigned int virq, unsigned int nr_irqs, > + void *args) > +{ > + struct rzg3s_pcie_msi *msi = domain->host_data; > + int hwirq; > + > + scoped_guard(mutex, &msi->map_lock) { > + hwirq = bitmap_find_free_region(msi->map, RZG3S_PCI_MSI_INT_NR, > + order_base_2(nr_irqs)); > + } > + > + if (hwirq < 0) > + return -ENOSPC; > + > + for (unsigned int i = 0; i < nr_irqs; i++) { > + irq_domain_set_info(domain, virq + i, hwirq + i, > + &rzg3s_pcie_msi_bottom_chip, > + domain->host_data, handle_edge_irq, NULL, > + NULL); > + } > + > + return 0; > +} > + > +static void rzg3s_pcie_msi_domain_free(struct irq_domain *domain, > + unsigned int virq, unsigned int nr_irqs) > +{ > + struct irq_data *d = irq_domain_get_irq_data(domain, virq); > + struct rzg3s_pcie_msi *msi = domain->host_data; > + > + guard(mutex)(&msi->map_lock); > + > + bitmap_release_region(msi->map, d->hwirq, order_base_2(nr_irqs)); > +} > + > +static const struct irq_domain_ops rzg3s_pcie_msi_domain_ops = { > + .alloc = rzg3s_pcie_msi_domain_alloc, > + .free = rzg3s_pcie_msi_domain_free, > +}; > + > +#define RZG3S_PCIE_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ > + MSI_FLAG_USE_DEF_CHIP_OPS | \ > + MSI_FLAG_NO_AFFINITY | \ > + MSI_FLAG_PCI_MSI_MASK_PARENT) > + > +#define RZG3S_PCIE_MSI_FLAGS_SUPPORTED (MSI_FLAG_MULTI_PCI_MSI | \ > + MSI_GENERIC_FLAGS_MASK) > + > +static const struct msi_parent_ops rzg3s_pcie_msi_parent_ops = { > + .required_flags = RZG3S_PCIE_MSI_FLAGS_REQUIRED, > + .supported_flags = RZG3S_PCIE_MSI_FLAGS_SUPPORTED, > + .bus_select_token = DOMAIN_BUS_PCI_MSI, > + .chip_flags = MSI_CHIP_FLAG_SET_ACK, > + .prefix = "RZG3S-", > + .init_dev_msi_info = msi_lib_init_dev_msi_info, > +}; > + > +static int rzg3s_pcie_msi_allocate_domains(struct rzg3s_pcie_msi *msi) > +{ > + struct rzg3s_pcie_host *host = rzg3s_msi_to_host(msi); > + struct device *dev = host->dev; > + struct irq_domain_info info = { > + .fwnode = dev_fwnode(dev), > + .ops = &rzg3s_pcie_msi_domain_ops, > + .size = RZG3S_PCI_MSI_INT_NR, > + .host_data = msi, > + }; > + > + msi->domain = msi_create_parent_irq_domain(&info, > + &rzg3s_pcie_msi_parent_ops); > + if (!msi->domain) > + return dev_err_probe(dev, -ENOMEM, > + "failed to create IRQ domain\n"); > + > + return 0; > +} > + > +static int rzg3s_pcie_msi_hw_setup(struct rzg3s_pcie_host *host) > +{ > + u8 regs = RZG3S_PCI_MSI_INT_NR / RZG3S_PCI_MSI_INT_PER_REG; > + struct rzg3s_pcie_msi *msi = &host->msi; > + > + /* > + * Set MSI window size. HW will set the window to > + * RZG3S_PCI_MSI_INT_NR * 4 bytes. > + */ > + writel_relaxed(FIELD_PREP(RZG3S_PCI_MSIRCVWMSKL_MASK, > + RZG3S_PCI_MSI_INT_NR - 1), > + host->axi + RZG3S_PCI_MSIRCVWMSKL); > + > + /* Set MSI window address and enable MSI window */ > + writel_relaxed(upper_32_bits(msi->window_base), > + host->axi + RZG3S_PCI_MSIRCVWADRU); > + writel_relaxed(lower_32_bits(msi->window_base) | > + RZG3S_PCI_MSIRCVWADRL_ENA | > + RZG3S_PCI_MSIRCVWADRL_MSG_DATA_ENA, > + host->axi + RZG3S_PCI_MSIRCVWADRL); > + > + /* Set MSI receive enable */ > + for (u8 reg_id = 0; reg_id < regs; reg_id++) { > + writel_relaxed(RZG3S_PCI_MSIRE_ENA, > + host->axi + RZG3S_PCI_MSIRE(reg_id)); > + } > + > + /* Enable message receive interrupts */ > + writel_relaxed(RZG3S_PCI_MSGRCVIE_MSG_RCV, > + host->axi + RZG3S_PCI_MSGRCVIE); > + > + /* Enable MSI */ > + rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIE, > + RZG3S_PCI_PINTRCVIE_MSI, > + RZG3S_PCI_PINTRCVIE_MSI); > + > + return 0; > +} > + > +static int rzg3s_pcie_msi_setup(struct rzg3s_pcie_host *host) > +{ > + size_t size = RZG3S_PCI_MSI_INT_NR * sizeof(u32); > + struct rzg3s_pcie_msi *msi = &host->msi; > + struct device *dev = host->dev; > + int id, ret; > + > + msi->pages = __get_free_pages(GFP_KERNEL | GFP_DMA, 0); > + if (!msi->pages) > + return -ENOMEM; > + > + msi->dma_addr = dma_map_single(dev, (void *)msi->pages, size * 2, > + DMA_BIDIRECTIONAL); > + if (dma_mapping_error(dev, msi->dma_addr)) { > + ret = -ENOMEM; > + goto free_pages; > + } > + > + /* > + * According to the RZ/G3S HW manual (Rev.1.10, section 34.4.5.2 Setting > + * the MSI Window) the MSI window needs to fall within one of the > + * enabled AXI windows. Find an enabled AXI window to setup the MSI > + * window. > + */ > + for (id = 0; id < RZG3S_MAX_WINDOWS; id++) { > + u64 base, basel, baseu; > + u64 mask, maskl, masku; > + > + basel = readl_relaxed(host->axi + RZG3S_PCI_AWBASEL(id)); > + /* Skip checking this AXI window if it's not enabled */ > + if (!(basel & RZG3S_PCI_AWBASEL_WIN_ENA)) > + continue; > + > + baseu = readl_relaxed(host->axi + RZG3S_PCI_AWBASEU(id)); > + base = baseu << 32 | basel; > + > + maskl = readl_relaxed(host->axi + RZG3S_PCI_AWMASKL(id)); > + masku = readl_relaxed(host->axi + RZG3S_PCI_AWMASKU(id)); > + mask = masku << 32 | maskl; > + > + if (msi->dma_addr < base || msi->dma_addr > base + mask) > + continue; > + > + break; > + } > + > + if (id == RZG3S_MAX_WINDOWS) { > + ret = -EINVAL; > + goto dma_unmap; > + } > + > + /* The MSI base address need to be aligned to the MSI size */ > + msi->window_base = ALIGN(msi->dma_addr, size); > + if (msi->window_base < msi->dma_addr) { > + ret = -EINVAL; > + goto dma_unmap; > + } > + > + rzg3s_pcie_msi_hw_setup(host); > + > + return 0; > + > +dma_unmap: > + dma_unmap_single(dev, msi->dma_addr, size * 2, DMA_BIDIRECTIONAL); > +free_pages: > + free_pages(msi->pages, 0); > + return ret; > +} > + > +static void rzg3s_pcie_msi_hw_teardown(struct rzg3s_pcie_host *host) > +{ > + u8 regs = RZG3S_PCI_MSI_INT_NR / RZG3S_PCI_MSI_INT_PER_REG; > + > + /* Disable MSI */ > + rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIE, > + RZG3S_PCI_PINTRCVIE_MSI, 0); > + > + /* Disable message receive interrupts */ > + rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_MSGRCVIE, > + RZG3S_PCI_MSGRCVIE_MSG_RCV, 0); > + > + /* Disable MSI receive enable */ > + for (u8 reg_id = 0; reg_id < regs; reg_id++) > + writel_relaxed(0, host->axi + RZG3S_PCI_MSIRE(reg_id)); > + > + /* Disable MSI window */ > + writel_relaxed(0, host->axi + RZG3S_PCI_MSIRCVWADRL); > +} > + > +static void rzg3s_pcie_teardown_msi(struct rzg3s_pcie_host *host) > +{ > + size_t size = RZG3S_PCI_MSI_INT_NR * sizeof(u32); > + struct rzg3s_pcie_msi *msi = &host->msi; > + > + rzg3s_pcie_msi_hw_teardown(host); > + > + free_irq(msi->irq, host); > + irq_domain_remove(msi->domain); > + > + /* Free unused memory */ > + dma_unmap_single(host->dev, msi->dma_addr, size * 2, DMA_BIDIRECTIONAL); > + free_pages(msi->pages, 0); > +} > + > +static int rzg3s_pcie_init_msi(struct rzg3s_pcie_host *host) > +{ > + struct platform_device *pdev = to_platform_device(host->dev); > + struct rzg3s_pcie_msi *msi = &host->msi; > + struct device *dev = host->dev; > + const char *devname; > + int irq, ret; > + > + ret = devm_mutex_init(dev, &msi->map_lock); > + if (ret) > + return ret; > + > + msi->irq = platform_get_irq_byname(pdev, "msi"); > + if (msi->irq < 0) > + return dev_err_probe(dev, irq ? irq : -EINVAL, > + "Failed to get MSI IRQ!\n"); irq is uninitialized. do you mean msi->irq? > + > + devname = devm_kasprintf(dev, GFP_KERNEL, "%s-msi", dev_name(dev)); > + if (!devname) > + return -ENOMEM; > + > + ret = rzg3s_pcie_msi_allocate_domains(msi); > + if (ret) > + return ret; > + > + /* > + * Don't use devm_request_irq() as the driver uses non-devm helpers > + * to control clocks. Mixing them may lead to subtle bugs. > + */ > + ret = request_irq(msi->irq, rzg3s_pcie_msi_irq, 0, devname, host); > + if (ret) { > + dev_err_probe(dev, ret, "Failed to request IRQ: %d\n", ret); > + goto free_domains; > + } > + > + ret = rzg3s_pcie_msi_setup(host); > + if (ret) { > + dev_err_probe(dev, ret, "Failed to setup MSI!\n"); > + goto free_irq; > + } > + > + return 0; > + > +free_irq: > + free_irq(msi->irq, host); > +free_domains: > + irq_domain_remove(msi->domain); > + return ret; > +} > + > +static void rzg3s_pcie_intx_irq_ack(struct irq_data *d) > +{ > + struct rzg3s_pcie_host *host = irq_data_get_irq_chip_data(d); > + > + guard(raw_spinlock_irqsave)(&host->hw_lock); > + > + rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIS, > + RZG3S_PCI_PINTRCVIS_INTX(d->hwirq), > + RZG3S_PCI_PINTRCVIS_INTX(d->hwirq)); > +} > + > +static int > +rzg3s_pcie_host_setup(struct rzg3s_pcie_host *host, > + int (*init_irqdomain)(struct rzg3s_pcie_host *host), > + void (*teardown_irqdomain)(struct rzg3s_pcie_host *host)) > +{ > + struct device *dev = host->dev; > + int ret; > + > + /* Set inbound windows */ > + ret = rzg3s_pcie_parse_map_dma_ranges(host); > + if (ret) > + return dev_err_probe(dev, ret, > + "Failed to set inbound windows!\n"); > + > + /* Set outbound windows */ > + ret = rzg3s_pcie_parse_map_ranges(host); > + if (ret) > + return dev_err_probe(dev, ret, > + "Failed to set outbound windows!\n"); > + > + ret = init_irqdomain(host); > + if (ret) > + return dev_err_probe(dev, ret, "Failed to init IRQ doamin\n"); typo doamin -> domain > + > + ret = rzg3s_pcie_host_init(host); > + if (ret) { > + dev_err_probe(dev, ret, "Failed to initialize the HW!\n"); > + goto teardown_irqdomain; > + } > + > + ret = rzg3s_pcie_set_max_link_speed(host); > + if (ret) > + dev_info(dev, "Failed to set max link speed\n"); > + > + msleep(PCIE_RESET_CONFIG_WAIT_MS); > + > + return 0; > + > +teardown_irqdomain: > + teardown_irqdomain(host); > + > + return ret; > +} Thanks, Alok