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Thu, 17 Oct 2024 11:51:37 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49HBpaP7022290 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 17 Oct 2024 11:51:36 GMT Received: from [10.214.67.37] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 17 Oct 2024 04:51:33 -0700 Message-ID: <32cf828b-91c8-4710-8943-f2d174ada53b@quicinc.com> Date: Thu, 17 Oct 2024 17:21:30 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/3] arm64: dts: qcom: sc7280: Add cpucp mbox node To: Bjorn Andersson CC: Sibi Sankar , Jassi Brar , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , , Konrad Dybcio , , , , "Ramakrishna Gottimukkula" References: <20240924050941.1251485-1-quic_kshivnan@quicinc.com> <20240924050941.1251485-4-quic_kshivnan@quicinc.com> Content-Language: en-US From: Shivnandan Kumar In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: RmnCT6i0ypCqfqcsorFjrrJEuIQB0qQr X-Proofpoint-ORIG-GUID: RmnCT6i0ypCqfqcsorFjrrJEuIQB0qQr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 adultscore=0 clxscore=1015 phishscore=0 spamscore=0 impostorscore=0 suspectscore=0 mlxlogscore=999 malwarescore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410170081 On 10/6/2024 8:05 AM, Bjorn Andersson wrote: > On Tue, Sep 24, 2024 at 10:39:41AM GMT, Shivnandan Kumar wrote: >> Add the CPUCP mailbox node required for communication with CPUCP. > > I'd like to see a description of why that's useful... > I will add in next patch set. > But perhaps more importantly, why are there no user(s) of this? > We will later add features such as BUS DCVS (memlat algorithm in CPUCP) and CPUCP logging based on this series. > Regards, > Bjorn > >> >> Signed-off-by: Shivnandan Kumar >> --- >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++++++++ >> 1 file changed, 8 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> index 3d8410683402..4b9b26a75c62 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> @@ -4009,6 +4009,14 @@ gem_noc: interconnect@9100000 { >> qcom,bcm-voters = <&apps_bcm_voter>; >> }; >> >> + cpucp_mbox: mailbox@17430000 { >> + compatible = "qcom,sc7280-cpucp-mbox"; >> + reg = <0 0x18590000 0 0x2000>, >> + <0 0x17C00000 0 0x10>; >> + interrupts = ; >> + #mbox-cells = <1>; >> + }; >> + >> system-cache-controller@9200000 { >> compatible = "qcom,sc7280-llcc"; >> reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, >> -- >> 2.25.1 >>