From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755591AbeEaQN4 (ORCPT ); Thu, 31 May 2018 12:13:56 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:35308 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755456AbeEaQNy (ORCPT ); Thu, 31 May 2018 12:13:54 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 3DC31602A8 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=okaya@codeaurora.org Subject: Re: [PATCH] PCI: Check for PCIe downtraining conditions To: "Alex G." , Alex_Gagniuc@Dellteam.com, bhelgaas@google.com Cc: Austin.Bolen@dell.com, Shyam.Iyer@dell.com, keith.busch@intel.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org References: <20180531150535.9684-1-mr.nuke.me@gmail.com> <28004506-24f0-6d10-2d1e-074e0483d2f9@codeaurora.org> <4e0611c872054e768daa96b302651db3@ausx13mps321.AMER.DELL.COM> <3b8a895b-3080-7ddb-cbfd-5aa972e9bf65@gmail.com> <35563ce3-e235-096c-4b9b-5f3664d67d0f@codeaurora.org> <093b2789-39a1-db9e-5783-b0488b3c9ccd@gmail.com> From: Sinan Kaya Message-ID: <32d58835-2f35-0b80-38d0-b9ff603619dd@codeaurora.org> Date: Thu, 31 May 2018 12:13:51 -0400 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.8.0 MIME-Version: 1.0 In-Reply-To: <093b2789-39a1-db9e-5783-b0488b3c9ccd@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 5/31/2018 12:01 PM, Alex G. wrote: >> PCI: Add pcie_print_link_status() to log link speed and whether it's limited > This one, I have, but it's not what I need. This looks at the available > bandwidth from root port to endpoint, whereas I'm only interested in > downtraining between endpoint and upstream port. I see what you are saying. With a little bit of effort, you can reuse the same code. Here is an attempt. You can probably extend pcie_bandwidth_available() to put an optional parent bridge device for your own use case and terminate the loop around here. https://elixir.bootlin.com/linux/v4.17-rc7/source/drivers/pci/pci.c#L5182 Then, you can use the existing code to achieve what you are looking for via pcie_print_link_status() by adding an optional parent parameter. bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap); bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width, *parent*); If parent parameter is NULL, code can walk all the way to root as it is doing today. If it is not, then will terminate the loop on the first iteration. -- Sinan Kaya Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.