From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B029613D2BC for ; Wed, 10 Apr 2024 07:57:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712735870; cv=none; b=S+4PNKnT8vgD3WbqkFByWnqboS7c2thCDwjjZXpwEwThh+0iH/k8O/bUX+zCWe/2/JlrdcWtLjv5DQYEbaD8JXezZalModSltuDus13hkK8bkpb/1j1gsyJteHinSg4yT9h4yQCm6hvTxwk8srciDOL+0TcyWUMu314J05kD9H0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712735870; c=relaxed/simple; bh=zSqtZOr6T9tpCLOf2qNdLQbDEt4yULfVFFG7OBHKU5Y=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=gCg70VFnO3kVWFlxlwktcoQXAl6LYqgoF/kPtk/IfX0GcGHefXBjYnsLIaP/94GJwdfqTFhowCN9L4eWyxsrRKTp4uDWCADyQbJLm3fWlLRWEajSgsUlmnecX42F1tOnmyY7uUf57NxXFsROrCm2oBffpXW3WbmCFWeYE9W9uAk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D915B1480; Wed, 10 Apr 2024 00:58:17 -0700 (PDT) Received: from [10.162.43.6] (a077893.blr.arm.com [10.162.43.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 81A413F766; Wed, 10 Apr 2024 00:57:42 -0700 (PDT) Message-ID: <32ddd2a6-22c6-49d2-aebb-da5a2e99748d@arm.com> Date: Wed, 10 Apr 2024 13:27:39 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 2/3] arm64: tlb: Improve __TLBI_VADDR_RANGE() Content-Language: en-US To: Gavin Shan , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: catalin.marinas@arm.com, will@kernel.org, akpm@linux-foundation.org, maz@kernel.org, oliver.upton@linux.dev, ryan.roberts@arm.com, apopple@nvidia.com, rananta@google.com, mark.rutland@arm.com, v-songbaohua@oppo.com, yangyicong@hisilicon.com, shahuang@redhat.com, yihyu@redhat.com, shan.gavin@gmail.com References: <20240405035852.1532010-1-gshan@redhat.com> <20240405035852.1532010-3-gshan@redhat.com> From: Anshuman Khandual In-Reply-To: <20240405035852.1532010-3-gshan@redhat.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 4/5/24 09:28, Gavin Shan wrote: > The macro returns the operand of TLBI RANGE instruction. A mask needs > to be applied to each individual field upon producing the operand, to > avoid the adjacent fields can interfere with each other when invalid > arguments have been provided. The code looks more tidy at least with > a mask and FIELD_PREP(). > > Suggested-by: Marc Zyngier > Signed-off-by: Gavin Shan This looks much better. Reviewed-by: Anshuman Khandual > --- > arch/arm64/include/asm/tlbflush.h | 29 ++++++++++++++++++----------- > 1 file changed, 18 insertions(+), 11 deletions(-) > > diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h > index a75de2665d84..243d71f7bc1f 100644 > --- a/arch/arm64/include/asm/tlbflush.h > +++ b/arch/arm64/include/asm/tlbflush.h > @@ -142,17 +142,24 @@ static inline unsigned long get_trans_granule(void) > * EL1, Inner Shareable". > * > */ > -#define __TLBI_VADDR_RANGE(baddr, asid, scale, num, ttl) \ > - ({ \ > - unsigned long __ta = (baddr); \ > - unsigned long __ttl = (ttl >= 1 && ttl <= 3) ? ttl : 0; \ > - __ta &= GENMASK_ULL(36, 0); \ > - __ta |= __ttl << 37; \ > - __ta |= (unsigned long)(num) << 39; \ > - __ta |= (unsigned long)(scale) << 44; \ > - __ta |= get_trans_granule() << 46; \ > - __ta |= (unsigned long)(asid) << 48; \ > - __ta; \ > +#define TLBIR_ASID_MASK GENMASK_ULL(63, 48) > +#define TLBIR_TG_MASK GENMASK_ULL(47, 46) > +#define TLBIR_SCALE_MASK GENMASK_ULL(45, 44) > +#define TLBIR_NUM_MASK GENMASK_ULL(43, 39) > +#define TLBIR_TTL_MASK GENMASK_ULL(38, 37) > +#define TLBIR_BADDR_MASK GENMASK_ULL(36, 0) > + > +#define __TLBI_VADDR_RANGE(baddr, asid, scale, num, ttl) \ > + ({ \ > + unsigned long __ta = 0; \ > + unsigned long __ttl = (ttl >= 1 && ttl <= 3) ? ttl : 0; \ > + __ta |= FIELD_PREP(TLBIR_BADDR_MASK, baddr); \ > + __ta |= FIELD_PREP(TLBIR_TTL_MASK, __ttl); \ > + __ta |= FIELD_PREP(TLBIR_NUM_MASK, num); \ > + __ta |= FIELD_PREP(TLBIR_SCALE_MASK, scale); \ > + __ta |= FIELD_PREP(TLBIR_TG_MASK, get_trans_granule()); \ > + __ta |= FIELD_PREP(TLBIR_ASID_MASK, asid); \ > + __ta; \ > }) > > /* These macros are used by the TLBI RANGE feature. */