From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.4 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE, SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0D5CC433DB for ; Tue, 2 Feb 2021 17:32:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 79B0964F4D for ; Tue, 2 Feb 2021 17:32:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237502AbhBBRbx (ORCPT ); Tue, 2 Feb 2021 12:31:53 -0500 Received: from mga06.intel.com ([134.134.136.31]:7379 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237482AbhBBR3e (ORCPT ); Tue, 2 Feb 2021 12:29:34 -0500 IronPort-SDR: yriaTroZyN9QN2rHOvE9DTotLabdtkGNmrgY20Rl/8grkrzc1EU8zotAjX8Vv5PlOflcKh7N+j evZZovEjtSiA== X-IronPort-AV: E=McAfee;i="6000,8403,9883"; a="242408116" X-IronPort-AV: E=Sophos;i="5.79,396,1602572400"; d="scan'208";a="242408116" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Feb 2021 09:27:47 -0800 IronPort-SDR: IR5PjwCStZQdpQtqcFgz7Wkc3sQluaVrplLmP+UXdn9IEf6Dj2MrBuPMBZhqPK9XXI78Fl3zZx Dee3RsH9FPoQ== X-IronPort-AV: E=Sophos;i="5.79,396,1602572400"; d="scan'208";a="370798487" Received: from ncruzgar-mobl.amr.corp.intel.com (HELO [10.212.75.122]) ([10.212.75.122]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Feb 2021 09:27:46 -0800 Subject: Re: [PATCH 2/3] soundwire: intel: add SDW_MASTER_QUIRKS_CLEAR_INITIAL_CLASH quirk To: Vinod Koul Cc: alsa-devel@alsa-project.org, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, ranjani.sridharan@linux.intel.com, hui.wang@canonical.com, srinivas.kandagatla@linaro.org, jank@cadence.com, sanyog.r.kale@intel.com, Bard Liao , rander.wang@linux.intel.com, bard.liao@intel.com References: <20210126083746.3238-1-yung-chuan.liao@linux.intel.com> <20210126083746.3238-3-yung-chuan.liao@linux.intel.com> <20210201104229.GY2771@vkoul-mobl> <0ed1c91b-09ca-dc6f-39d1-850d12f4f9c4@linux.intel.com> <20210202044139.GH2771@vkoul-mobl> From: Pierre-Louis Bossart Message-ID: <32df8d27-3393-f049-a493-4ba43962d490@linux.intel.com> Date: Tue, 2 Feb 2021 10:53:04 -0600 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20210202044139.GH2771@vkoul-mobl> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org >>>> + prop->quirks = SDW_MASTER_QUIRKS_CLEAR_INITIAL_CLASH; >>> >>> Should this not be last 'enabling' the quirk patch in series :) >> >> Sorry, I don't understand the comment. Do you mind clarifying Vinod? > > Sure, I would like to series built as, first defining the quirk > along/followed by bus changes. Then the last patch should be intel > controller changes and setting the quirks (like above) in the last > patch. > > Let me know if you would need further clarification Got it, thanks.