From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754956AbdEENxt (ORCPT ); Fri, 5 May 2017 09:53:49 -0400 Received: from mail-pg0-f51.google.com ([74.125.83.51]:33324 "EHLO mail-pg0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753979AbdEENxp (ORCPT ); Fri, 5 May 2017 09:53:45 -0400 Subject: Re: [PATCH v3 3/7] ACPICA: IORT: Add Cavium ThunderX2 SMMUv3 model definition. To: Geetha sowjanya , will.deacon@arm.com, robin.murphy@arm.com, lorenzo.pieralisi@arm.com, sudeep.holla@arm.com, iommu@lists.linux-foundation.org References: <1493986091-30521-1-git-send-email-gakula@caviumnetworks.com> <1493986091-30521-4-git-send-email-gakula@caviumnetworks.com> Cc: jcm@redhat.com, linux-kernel@vger.kernel.org, robert.richter@cavium.com, catalin.marinas@arm.com, sgoutham@cavium.com, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, geethasowjanya.akula@gmail.com, linu.cherian@cavium.com, Charles.Garcia-Tobin@arm.com, Geetha Sowjanya From: Hanjun Guo Message-ID: <330d0438-f9ed-ef65-8ffd-d556d149b4e1@linaro.org> Date: Fri, 5 May 2017 21:53:26 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 MIME-Version: 1.0 In-Reply-To: <1493986091-30521-4-git-send-email-gakula@caviumnetworks.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2017/5/5 20:08, Geetha sowjanya wrote: > From: Linu Cherian > > Add SMMUv3 model definition for ThunderX2. > > Signed-off-by: Linu Cherian > Signed-off-by: Geetha Sowjanya > --- > include/acpi/actbl2.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h > index faa9f2c..76a6f5d 100644 > --- a/include/acpi/actbl2.h > +++ b/include/acpi/actbl2.h > @@ -779,6 +779,8 @@ struct acpi_iort_smmu { > #define ACPI_IORT_SMMU_CORELINK_MMU400 0x00000002 /* ARM Corelink MMU-400 */ > #define ACPI_IORT_SMMU_CORELINK_MMU500 0x00000003 /* ARM Corelink MMU-500 */ > > +#define ACPI_IORT_SMMU_V3_CAVIUM_CN99XX 0x00000002 /* Cavium ThunderX2 SMMUv3 */ There are some other model numbers in the unreleased spec, I think we need to wait for the updated IORT spec to be released. Thanks Hanjun