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[88.156.142.67]) by smtp.gmail.com with ESMTPSA id n20-20020a05651203f400b004a44ffb1023sm3436267lfq.57.2022.12.30.02.41.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 30 Dec 2022 02:41:11 -0800 (PST) Message-ID: <33196eef-b1d5-8dd2-7c59-16a73327e8c0@linaro.org> Date: Fri, 30 Dec 2022 11:41:10 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v3 01/19] dt-bindings: ARM: MediaTek: Add new document bindings of MT8188 clock Content-Language: en-US To: "Garmin.Chang" , Matthias Brugger , Rob Herring , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Richard Cochran Cc: Project_Global_Chrome_Upstream_Group@mediatek.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, netdev@vger.kernel.org References: <20221230073357.18503-1-Garmin.Chang@mediatek.com> <20221230073357.18503-2-Garmin.Chang@mediatek.com> From: Krzysztof Kozlowski In-Reply-To: <20221230073357.18503-2-Garmin.Chang@mediatek.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 30/12/2022 08:33, Garmin.Chang wrote: > Add the new binding documentation for system clock > and functional clock on MediaTek MT8188. > Subject: drop second, redundant "document bindings of". > Signed-off-by: Garmin.Chang > --- > .../arm/mediatek/mediatek,mt8188-clock.yaml | 71 ++ > .../mediatek/mediatek,mt8188-sys-clock.yaml | 55 ++ > .../dt-bindings/clock/mediatek,mt8188-clk.h | 733 ++++++++++++++++++ > 3 files changed, 859 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188-clock.yaml > create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188-sys-clock.yaml > create mode 100644 include/dt-bindings/clock/mediatek,mt8188-clk.h > > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188-clock.yaml > new file mode 100644 > index 000000000000..6654cead71f6 > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188-clock.yaml Clock controllers do not go to arm but to clock. It's so suprising directory that I missed to notice it in v1... Why putting it in some totally irrelevant directory? > @@ -0,0 +1,71 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8188-clock.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek Functional Clock Controller for MT8188 > + > +maintainers: > + - Garmin Chang > + > +description: | > + The clock architecture in MediaTek like below > + PLLs --> > + dividers --> > + muxes > + --> > + clock gate > + > + The devices provide clock gate control in different IP blocks. > + > +properties: > + compatible: > + enum: > + - mediatek,mt8188-adsp-audio26m > + - mediatek,mt8188-imp-iic-wrap-c > + - mediatek,mt8188-imp-iic-wrap-en > + - mediatek,mt8188-imp-iic-wrap-w > + - mediatek,mt8188-mfgcfg > + - mediatek,mt8188-vppsys0 > + - mediatek,mt8188-wpesys > + - mediatek,mt8188-wpesys-vpp0 > + - mediatek,mt8188-vppsys1 > + - mediatek,mt8188-imgsys > + - mediatek,mt8188-imgsys-wpe1 > + - mediatek,mt8188-imgsys-wpe2 > + - mediatek,mt8188-imgsys-wpe3 > + - mediatek,mt8188-imgsys1-dip-top > + - mediatek,mt8188-imgsys1-dip-nr > + - mediatek,mt8188-ipesys > + - mediatek,mt8188-camsys > + - mediatek,mt8188-camsys-rawa > + - mediatek,mt8188-camsys-yuva > + - mediatek,mt8188-camsys-rawb > + - mediatek,mt8188-camsys-yuvb > + - mediatek,mt8188-ccusys > + - mediatek,mt8188-vdecsys-soc > + - mediatek,mt8188-vdecsys > + - mediatek,mt8188-vencsys > + > + reg: > + maxItems: 1 > + > + '#clock-cells': > + const: 1 > + > +required: > + - compatible > + - reg > + - '#clock-cells' > + > +additionalProperties: false > + > +examples: > + - | > + clock-controller@11283000 { > + compatible = "mediatek,mt8188-imp-iic-wrap-c"; > + reg = <0x11283000 0x1000>; > + #clock-cells = <1>; > + }; > + > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188-sys-clock.yaml > new file mode 100644 > index 000000000000..2b28df1ff895 > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188-sys-clock.yaml Wrong directory. > @@ -0,0 +1,55 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8188-sys-clock.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek System Clock Controller for MT8188 > + > +maintainers: > + - Garmin Chang > + > +description: | > + The clock architecture in MediaTek like below > + PLLs --> > + dividers --> > + muxes > + --> > + clock gate > + > + The apmixedsys provides most of PLLs which generated from SoC 26m. > + The topckgen provides dividers and muxes which provide the clock source to other IP blocks. > + The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks. > + The mcusys provides mux control to select the clock source in AP MCU. > + The device nodes also provide the system control capacity for configuration. > + > +properties: > + compatible: > + items: > + - enum: > + - mediatek,mt8188-topckgen > + - mediatek,mt8188-infracfg-ao > + - mediatek,mt8188-apmixedsys > + - mediatek,mt8188-pericfg-ao > + - const: syscon > + > + reg: > + maxItems: 1 > + > + '#clock-cells': > + const: 1 > + > +required: > + - compatible > + - reg > + - '#clock-cells' > + > +additionalProperties: false > + > +examples: > + - | > + syscon@10000000 { clock-controller > + compatible = "mediatek,mt8188-topckgen", "syscon"; > + reg = <0x10000000 0x1000>; > + #clock-cells = <1>; Best regards, Krzysztof