From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B9D6145348 for ; Tue, 17 Feb 2026 07:01:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771311676; cv=none; b=alt+n2WUVp9ezZ/LTAPfhgSY+qJswSdxycrdqDS+M1R6qL67k2IMHhKLHfnyA5Ggc9eKjd1mk2f4BdIYfXI7PF1a82T7cXPjxtAale1d1tUHQ1Jre6JdvP3BcIcSswtPW/Ql0IA09HF2aPwKrDyIIHvCDMTHEwhWQcBDzmFJad0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771311676; c=relaxed/simple; bh=3bYNq6tiMxw2Y93rWvazq/YhtDUy17/SyOh/jHb/WsY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=eNP9iZHjUgDzk9xk4/QohwUXcCWfNPoCwqkhbmEwrjuyV1ctNndOjdKZ6a4r6oeCcONArAYqAZSQADeX17GU7jRmEe7hIiseRJaYGFrVhZl/3aXMvkA/4otdmuvNh/cCa0KGT0VCd3uzBkYr7NbiLMX7kpFquOazvA4VPTyKJQw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=uY3/kyKF; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="uY3/kyKF" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Type:Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To; bh=7whLfHtrwixcpFYAilK93BQ7JEuEzGUjhW1Qjky9ZDI=; b=uY3/kyKFYgVpqLuI1xZzHdJiMN tio6JDD4VrwqvbmuVLCB5dge4bc7R58r+7tzG2vodO7t2rPSPeOe+743AyrcBW1lJYHqtaXifZ8ts CM7HxDhT0JuotzNf2JsPCUh5nkbxNfzQ/wWURVFrH4cr5SJls5V7C4D28ejjqMIehl51qW93LcGoA FVLbbTnyTP02u+9HETXsXc7A21zEgOqeFGPEN2NUAkQB+bke7htZ9SqR7ZQvHXzjPaUmyEwifjoCu gUIajRww4N9KCaETy9MvQcSJcLrhN3YbofUAWgcmW5745WXEAsq8tKtG28uQdQnnvtzfcOTkLgfND glq/b5SQ==; From: Heiko =?UTF-8?B?U3TDvGJuZXI=?= To: dri-devel@lists.freedesktop.org, Ross Cawston Cc: linux-kernel@vger.kernel.org, tomeu@tomeuvizoso.net, ogabbay@kernel.org, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, jeff.hugo@oss.qualcomm.com, jani.nikula@intel.com, me@brighamcampbell.com, Ross Cawston Subject: Re: [PATCH] accel/rocket: Add per-task flags and interrupt mask for flexible job handling Date: Tue, 17 Feb 2026 08:00:58 +0100 Message-ID: <3327246.2IRrRt1zHL@diego> In-Reply-To: <20260216183819.99991-1-ross@r-sc.ca> References: <20260216183819.99991-1-ross@r-sc.ca> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Am Montag, 16. Februar 2026, 19:38:19 Mitteleurop=C3=A4ische Normalzeit sch= rieb Ross Cawston: > The Rocket NPU supports multiple task types: > - Convolutional workloads that use CNA, Core, and DPU blocks > - Standalone post-processing (PPU) tasks such as pooling and element-wise= operations > - Pipelined DPU=E2=86=92PPU workloads >=20 > The current driver has several limitations that prevent correct execution= of > non-convolutional workloads and multi-core operation: >=20 > - CNA and Core S_POINTER registers are always initialized, re-arming them > with stale state from previous jobs and corrupting standalone DPU/PPU t= asks. > - Completion is hard-coded to wait only for DPU interrupts, causing PPU-o= nly > or DPU=E2=86=92PPU pipeline jobs to time out. > - Ping-pong mode is unconditionally enabled, which is unnecessary for > single-task jobs. > - Non-zero cores hang because the vendor-specific "extra bit" (bit 28 =C3= =97 core > index) in S_POINTER is not set; the BSP sets this via MMIO because user= space > cannot know which core the scheduler will select. > - Timeout and IRQ debugging information is minimal. >=20 > This patch introduces two new per-task fields to struct rocket_task: >=20 > - u32 int_mask: specifies which block completion interrupts signal task d= one > (DPU_0|DPU_1 for convolutional/standalone DPU, PPU_0|PPU_1 for PPU task= s). > Zero defaults to DPU_0|DPU_1 for backward compatibility. > - u32 flags: currently used for ROCKET_TASK_NO_CNA_CORE to indicate stand= alone > DPU/PPU tasks that must not touch CNA/Core state. >=20 > Additional changes: > - Only initialize CNA and Core S_POINTER (with the required per-core extr= a bit) > when ROCKET_TASK_NO_CNA_CORE is not set. > - Set the per-core extra bit via MMIO to fix hangs on non-zero cores. > - Enable ping-pong mode only when the job contains multiple tasks. > - Mask and clear interrupts according to the task's int_mask. > - Accept both DPU and PPU completion interrupts in the IRQ handler. > - Minor error-path fix in GEM object creation (check error after unlocking > mm_lock). >=20 > These changes, derived from vendor BSP behavior, enable correct execution > of PPU-only tasks, pipelined workloads, and reliable multi-core operation > while preserving backward compatibility. Missing a Signed-off-by line. Please see https://www.kernel.org/doc/html/latest/process/submitting-patches.html#deve= loper-s-certificate-of-origin-1-1 Heiko > --- > drivers/accel/rocket/rocket_gem.c | 2 + > drivers/accel/rocket/rocket_job.c | 99 +++++++++++++++++++++++++------ > drivers/accel/rocket/rocket_job.h | 2 + > include/uapi/drm/rocket_accel.h | 30 ++++++++++ > 4 files changed, 115 insertions(+), 18 deletions(-)