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X-CSE-ConnectionGUID: 4NLfqXQUSqOPPpGvSaD+Yw== X-CSE-MsgGUID: q70bHFYIQE6lS/ArafhTEA== X-IronPort-AV: E=McAfee;i="6700,10204,11192"; a="24420718" X-IronPort-AV: E=Sophos;i="6.10,221,1719903600"; d="scan'208";a="24420718" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Sep 2024 17:23:19 -0700 X-CSE-ConnectionGUID: xbJ5DSq+TsihI8G/1gHitA== X-CSE-MsgGUID: jzzAgGozTW2yEHCeAGNJ/w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,221,1719903600"; d="scan'208";a="67527291" Received: from dgramcko-desk.amr.corp.intel.com (HELO [10.124.223.221]) ([10.124.223.221]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Sep 2024 17:23:18 -0700 Message-ID: <3328e53d-b0f2-4516-a6a6-51ca33642683@intel.com> Date: Wed, 11 Sep 2024 17:22:59 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 1/1] x86/fred: Clear the WFE bit in missing-ENDBRANCH #CP To: "Xin Li (Intel)" , linux-kernel@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com References: <20240911231929.2632698-1-xin@zytor.com> From: Dave Hansen Content-Language: en-US Autocrypt: addr=dave.hansen@intel.com; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 9/11/24 16:19, Xin Li (Intel) wrote: > +/* > + * The WFE (WAIT_FOR_ENDBRANCH) bit in the augmented CS of FRED stack frame is > + * set to 1 in missing-ENDBRANCH #CP exceptions. I think there's a bit of relatively irrelevant info in there. For instance, I don't think it's super important to mention that FRED is involved and where the WFE bit is in memory. FRED's involvement is kinda a no-brainer from the whole X86_FEATURE_FRED thing, and if you're reading exception handler code and don't know that 'regs' is on the stack, this probably isn't the place to explain that. > + * If the WFE bit is left as 1, the CPU will generate another missing-ENDBRANCH > + * #CP because the indirect branch tracker will be set in the WAIT_FOR_ENDBRANCH > + * state upon completion of the following ERETS instruction and the CPU will > + * restart from the IP that just caused a previous missing-ENDBRANCH #CP. > + * > + * Clear the WFE bit to avoid dead looping due to the above reason. > + */ > +static void ibt_clear_fred_wfe(struct pt_regs *regs) > +{ > + if (cpu_feature_enabled(X86_FEATURE_FRED)) > + regs->fred_cs.wfe = 0; > +} Can I suggest a slightly different comment? /* * WFE==1 (WAIT_FOR_ENDBRANCH) means that the CPU expects the next ERETS * to jump to an ENDBR instruction. If the ENDBR is missing, the CPU * raises a #CP. * * Clear WFE to avoid that #CP. * * Use this function in a #CP handler to effectively give the next * ERETS a free pass to ignore IBT for a single instruction. */ I think original comment really needs a "How do I use this?" sentence or two. A comment at the call site also wouldn't hurt: if (unlikely(regs->ip == (unsigned long)&ibt_selftest_noendbr)){ regs->ax = 0; + /* Disable IBT enforcement for one exception return: */ + ibt_clear_fred_wfe(regs); return; } I'm finding it kinda hard to concisely differentiate between the "disable IBT at one ERETS" and "disable IBT forever", but I hope this sounds good to folks.