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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2beb58b2d47sm203898135ad.45.2026.05.27.20.03.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 27 May 2026 20:03:50 -0700 (PDT) Message-ID: <332c5b1e-8b70-4902-99f3-536dfe8e32bf@oss.qualcomm.com> Date: Thu, 28 May 2026 11:03:45 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 2/7] clk: qcom: Add generic clkref_en support To: Qiang Yu , Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, krishna.chundru@oss.qualcomm.com References: <20260527-tcsr_qref_0527-v4-0-ded83866c9d9@oss.qualcomm.com> <20260527-tcsr_qref_0527-v4-2-ded83866c9d9@oss.qualcomm.com> Content-Language: en-US From: Jie Gan In-Reply-To: <20260527-tcsr_qref_0527-v4-2-ded83866c9d9@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTI4MDAyNyBTYWx0ZWRfX1cE/DRyvqkaB b3Ck8jzT6M3DwjA7RB6jg2IhkhdQAd2K+aRDxyST1PeP9VMfcEXBBznzJBEfc4bsaHs0d28EYRd hKMNjx6qfxqv1gUjZg/dGkEJ0gz4pbGJABAMUOdP7QS+yclMFyFaoDq/gDLijx620WXBEp3zY+R MQJ1bjyUuWsXzDXZlGS6NA9hPcmgZeYmiMUMWGN4IeLcJg853vHgkvGvGZ+Ued4gLtF3OCvwce+ iEbjuzkCR3xzRoS7nDkzgNzVFCySdjqvGuhLD8ZFWoiphiOeS3p2/Tc/YKge4HrE31jnA/9osg5 xSrKQ+qvt97o4KTV5PGLcL1o2R/ZNoevOtkdwXnCg72O9e5UHP9YMYJb6ZeA+VTfeR5BFN0qDNm wnoo+KC8HIDJNqSfdqL75CTF0/vNQCSd5PlG9Nub5JLsKQEPM68Rr3yo47g/MdsAleLV+RChLfz uOT+pOx3jhx/Yxw50Xw== X-Authority-Analysis: v=2.4 cv=feidDUQF c=1 sm=1 tr=0 ts=6a17b098 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=Vq0jQWeKcoOPcsz1E3gA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-GUID: yyaNDm5dAeKJ37JNtj2kxGOMeF2t0D9_ X-Proofpoint-ORIG-GUID: yyaNDm5dAeKJ37JNtj2kxGOMeF2t0D9_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-05-27_05,2026-05-26_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 priorityscore=1501 phishscore=0 suspectscore=0 bulkscore=0 impostorscore=0 adultscore=0 lowpriorityscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2605280027 On 5/28/2026 10:29 AM, Qiang Yu wrote: > Before XO refclk is distributed to PCIe/USB/eDP PHYs, it passes through > a QREF block. QREF is powered by dedicated LDO rails, and the clkref_en > register controls whether refclk is gated through to the PHY side. > > These clkref controls are different from typical GCC branch clocks: > - only a single enable bit is present, without branch-style config bits > - regulators must be voted before enable and unvoted after disable > > Model this as a dedicated clk_ref clock type with custom clk_ops instead > of reusing struct clk_branch semantics. > > Also provide a common registration/probe API so the same clkref model > can be reused regardless of where clkref_en registers are placed, e.g. > TCSR on glymur and TLMM on SM8750. > > Signed-off-by: Qiang Yu > --- > drivers/clk/qcom/Makefile | 1 + > drivers/clk/qcom/clk-ref.c | 205 +++++++++++++++++++++++++++++++++++++++++++++ > include/linux/clk/qcom.h | 69 +++++++++++++++ > 3 files changed, 275 insertions(+) > > diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile > index e100cfd6a52d..c5b02360861d 100644 > --- a/drivers/clk/qcom/Makefile > +++ b/drivers/clk/qcom/Makefile > @@ -8,6 +8,7 @@ clk-qcom-y += clk-pll.o > clk-qcom-y += clk-rcg.o > clk-qcom-y += clk-rcg2.o > clk-qcom-y += clk-branch.o > +clk-qcom-y += clk-ref.o > clk-qcom-y += clk-regmap-divider.o > clk-qcom-y += clk-regmap-mux.o > clk-qcom-y += clk-regmap-mux-div.o > diff --git a/drivers/clk/qcom/clk-ref.c b/drivers/clk/qcom/clk-ref.c > new file mode 100644 > index 000000000000..213c0f58bb36 > --- /dev/null > +++ b/drivers/clk/qcom/clk-ref.c > @@ -0,0 +1,205 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2026, Qualcomm Technologies, Inc. and/or its subsidiaries. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define QCOM_CLK_REF_EN_MASK BIT(0) > + > +struct qcom_clk_ref_provider { > + struct qcom_clk_ref *refs; > + size_t num_refs; > +}; > + > +static inline struct qcom_clk_ref *to_qcom_clk_ref(struct clk_hw *hw) > +{ > + return container_of(hw, struct qcom_clk_ref, hw); > +} > + > +static const struct clk_parent_data qcom_clk_ref_parent_data = { > + .index = 0, > +}; > + > +static int qcom_clk_ref_prepare(struct clk_hw *hw) > +{ > + struct qcom_clk_ref *rclk = to_qcom_clk_ref(hw); > + int ret; > + > + if (!rclk->desc.num_regulators) > + return 0; > + > + ret = regulator_bulk_enable(rclk->desc.num_regulators, rclk->regulators); > + if (ret) > + pr_err("Failed to enable regulators for %s: %d\n", > + clk_hw_get_name(hw), ret); > + > + return ret; > +} > + > +static void qcom_clk_ref_unprepare(struct clk_hw *hw) > +{ > + struct qcom_clk_ref *rclk = to_qcom_clk_ref(hw); > + > + if (rclk->desc.num_regulators) > + regulator_bulk_disable(rclk->desc.num_regulators, rclk->regulators); > +} > + > +static int qcom_clk_ref_enable(struct clk_hw *hw) > +{ > + struct qcom_clk_ref *rclk = to_qcom_clk_ref(hw); > + int ret; > + > + ret = regmap_update_bits(rclk->regmap, rclk->desc.offset, QCOM_CLK_REF_EN_MASK, > + QCOM_CLK_REF_EN_MASK); > + if (ret) > + return ret; > + > + udelay(10); try usleep_range instead of udelay for better power consumption. > + > + return 0; > +} > + > +static void qcom_clk_ref_disable(struct clk_hw *hw) > +{ > + struct qcom_clk_ref *rclk = to_qcom_clk_ref(hw); > + > + regmap_update_bits(rclk->regmap, rclk->desc.offset, QCOM_CLK_REF_EN_MASK, 0); > + udelay(10); > +} > + > +static int qcom_clk_ref_is_enabled(struct clk_hw *hw) > +{ > + struct qcom_clk_ref *rclk = to_qcom_clk_ref(hw); > + u32 val; > + int ret; > + > + ret = regmap_read(rclk->regmap, rclk->desc.offset, &val); > + if (ret) > + return ret; regmap_read returns a negative error code on failure, but the clk_ops.is_enabled() treats the non-zero value as enabled. Thanks, Jie > + > + return !!(val & QCOM_CLK_REF_EN_MASK); > +} > + > +static const struct clk_ops qcom_clk_ref_ops = { > + .prepare = qcom_clk_ref_prepare, > + .unprepare = qcom_clk_ref_unprepare, > + .enable = qcom_clk_ref_enable, > + .disable = qcom_clk_ref_disable, > + .is_enabled = qcom_clk_ref_is_enabled, > +}; > + > +static int qcom_clk_ref_register(struct device *dev, struct regmap *regmap, > + struct qcom_clk_ref *clk_refs, > + const struct qcom_clk_ref_desc *descs, > + size_t num_clk_refs) > +{ > + const struct qcom_clk_ref_desc *desc; > + struct qcom_clk_ref *clk_ref; > + size_t clk_idx; > + unsigned int i; > + int ret; > + > + for (clk_idx = 0; clk_idx < num_clk_refs; clk_idx++) { > + clk_ref = &clk_refs[clk_idx]; > + desc = &descs[clk_idx]; > + > + if (!desc->name) > + continue; > + > + clk_ref->regmap = regmap; > + clk_ref->desc = *desc; > + > + if (clk_ref->desc.num_regulators) { > + clk_ref->regulators = devm_kcalloc(dev, clk_ref->desc.num_regulators, > + sizeof(*clk_ref->regulators), > + GFP_KERNEL); > + if (!clk_ref->regulators) > + return -ENOMEM; > + > + for (i = 0; i < clk_ref->desc.num_regulators; i++) > + clk_ref->regulators[i].supply = > + clk_ref->desc.regulator_names[i]; > + > + ret = devm_regulator_bulk_get(dev, clk_ref->desc.num_regulators, > + clk_ref->regulators); > + if (ret) > + return dev_err_probe(dev, ret, > + "Failed to get regulators for %s\n", > + clk_ref->desc.name); > + } > + > + clk_ref->init_data.name = clk_ref->desc.name; > + clk_ref->init_data.parent_data = &qcom_clk_ref_parent_data; > + clk_ref->init_data.num_parents = 1; > + clk_ref->init_data.ops = &qcom_clk_ref_ops; > + clk_ref->hw.init = &clk_ref->init_data; > + > + ret = devm_clk_hw_register(dev, &clk_ref->hw); > + if (ret) > + return ret; > + } > + > + return 0; > +} > + > +static struct clk_hw *qcom_clk_ref_provider_get(struct of_phandle_args *clkspec, void *data) > +{ > + struct qcom_clk_ref_provider *provider = data; > + unsigned int idx = clkspec->args[0]; > + > + if (idx >= provider->num_refs) > + return ERR_PTR(-EINVAL); > + > + if (!provider->refs[idx].regmap) > + return ERR_PTR(-ENOENT); > + > + return &provider->refs[idx].hw; > +} > + > +int qcom_clk_ref_probe(struct platform_device *pdev, > + const struct regmap_config *config, > + const struct qcom_clk_ref_desc *descs, > + size_t num_clk_refs) > +{ > + struct qcom_clk_ref_provider *provider; > + struct device *dev = &pdev->dev; > + struct regmap *regmap; > + void __iomem *base; > + int ret; > + > + base = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(base)) > + return PTR_ERR(base); > + > + regmap = devm_regmap_init_mmio(dev, base, config); > + if (IS_ERR(regmap)) > + return PTR_ERR(regmap); > + > + provider = devm_kzalloc(dev, sizeof(*provider), GFP_KERNEL); > + if (!provider) > + return -ENOMEM; > + > + provider->refs = devm_kcalloc(dev, num_clk_refs, sizeof(*provider->refs), > + GFP_KERNEL); > + if (!provider->refs) > + return -ENOMEM; > + > + provider->num_refs = num_clk_refs; > + > + ret = qcom_clk_ref_register(dev, regmap, provider->refs, descs, > + provider->num_refs); > + if (ret) > + return ret; > + > + return devm_of_clk_add_hw_provider(dev, qcom_clk_ref_provider_get, provider); > +} > +EXPORT_SYMBOL_GPL(qcom_clk_ref_probe); > diff --git a/include/linux/clk/qcom.h b/include/linux/clk/qcom.h > new file mode 100644 > index 000000000000..09e2e3178cfb > --- /dev/null > +++ b/include/linux/clk/qcom.h > @@ -0,0 +1,69 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (c) 2026, Qualcomm Technologies, Inc. and/or its subsidiaries. > + */ > + > +#ifndef __LINUX_CLK_QCOM_H > +#define __LINUX_CLK_QCOM_H > + > +#include > +#include > +#include > +#include > +#include > + > +struct device; > +struct platform_device; > +struct regulator_bulk_data; > + > +/** > + * struct qcom_clk_ref_desc - descriptor for a clkref_en gate clock > + * @name: clock name exposed to the common clock framework > + * @offset: clkref_en register offset from the block base > + * @regulator_names: optional supply names enabled while preparing the clock > + * @num_regulators: number of entries in @regulator_names > + */ > +struct qcom_clk_ref_desc { > + const char *name; > + u32 offset; > + const char * const *regulator_names; > + unsigned int num_regulators; > +}; > + > +/** > + * struct qcom_clk_ref - per-clock data for a clkref_en gate clock > + * @hw: common clock framework hardware clock handle > + * @init_data: common clock framework registration data > + * @regmap: register map backing the clkref_en register > + * @desc: clock descriptor copied at registration time > + * @regulators: optional bulk regulator handles for @desc.regulator_names > + */ > +struct qcom_clk_ref { > + struct clk_hw hw; > + struct clk_init_data init_data; > + struct regmap *regmap; > + struct qcom_clk_ref_desc desc; > + struct regulator_bulk_data *regulators; > +}; > + > +#if IS_ENABLED(CONFIG_COMMON_CLK_QCOM) > + > +int qcom_clk_ref_probe(struct platform_device *pdev, > + const struct regmap_config *config, > + const struct qcom_clk_ref_desc *descs, > + size_t num_clk_refs); > + > +#else > + > +static inline int > +qcom_clk_ref_probe(struct platform_device *pdev, > + const struct regmap_config *config, > + const struct qcom_clk_ref_desc *descs, > + size_t num_clk_refs) > +{ > + return -EOPNOTSUPP; > +} > + > +#endif > + > +#endif >