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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9b3a081d59sm95061466b.189.2024.10.25.11.17.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 25 Oct 2024 11:17:06 -0700 (PDT) Message-ID: <333948f0-44ff-424a-8d38-5fba719d2aeb@oss.qualcomm.com> Date: Fri, 25 Oct 2024 20:17:03 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 3/5] dmaengine: qcom: gpi: Add provision to support TRE size as the fourth argument of dma-cells property To: Jyothi Kumar Seerapu , Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Andi Shyti , Sumit Semwal , =?UTF-8?Q?Christian_K=C3=B6nig?= Cc: cros-qcom-dts-watchers@chromium.org, linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-media@vger.kernel.org, dri-devel@lists.freedesktop.org, linaro-mm-sig@lists.linaro.org, quic_msavaliy@quicinc.com, quic_vtanuku@quicinc.com References: <20241015120750.21217-1-quic_jseerapu@quicinc.com> <20241015120750.21217-4-quic_jseerapu@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20241015120750.21217-4-quic_jseerapu@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: DPjzJEjtlkPbiOz0axtRNIg0DBRawGsV X-Proofpoint-GUID: DPjzJEjtlkPbiOz0axtRNIg0DBRawGsV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 impostorscore=0 bulkscore=0 mlxlogscore=999 malwarescore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 mlxscore=0 priorityscore=1501 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410250140 On 15.10.2024 2:07 PM, Jyothi Kumar Seerapu wrote: > The current GPI driver hardcodes the channel TRE (Transfer Ring Element) > size to 64. For scenarios requiring high performance with multiple > messages in a transfer, use Block Event Interrupt (BEI). > This method triggers interrupt after specific message transfers and > the last message transfer, effectively reducing the number of interrupts. > For multiple transfers utilizing BEI, a channel TRE size of 64 is > insufficient and may lead to transfer failures, indicated by errors > related to unavailable memory space. > > Added provision to modify the channel TRE size via the device tree. > The Default channel TRE size is set to 64, but this value can update > in the device tree which will then be parsed by the GPI driver. > > Signed-off-by: Jyothi Kumar Seerapu > --- 1. Is the total memory pool for these shared? 2. Is there any scenario where we want TRE size to be lower and not higher? Are there any drawbacks to always keeping them at SOME_MAX_VALUE? 3. Is this something we should configure at boot time (in firmware)? Perhaps this could be decided based on client device settings (which may or may not require adding some field in the i2c framework) Konrad