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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-76e8ab7b2dfsm2046761b3a.38.2025.08.19.23.17.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 19 Aug 2025 23:17:51 -0700 (PDT) Message-ID: <33468410-69e5-4144-88e0-cc34a736c0e4@oss.qualcomm.com> Date: Wed, 20 Aug 2025 14:17:44 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/4] phy: qcom: qmp-pcie: Add support for Glymur PCIe Gen5x4 PHY To: Dmitry Baryshkov Cc: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Bjorn Andersson , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, konrad.dybcio@oss.qualcomm.com, qiang.yu@oss.qualcomm.com, Prudhvi Yarlagadda References: <20250819-glymur_pcie5-v1-0-2ea09f83cbb0@oss.qualcomm.com> <20250819-glymur_pcie5-v1-4-2ea09f83cbb0@oss.qualcomm.com> <6zlydkdgmowqg7cv5eeoaf7mrpnhzokyvhh5xasvznqaxnhdji@xol3jiz2lzld> Content-Language: en-US From: "Wenbin Yao (Consultant)" In-Reply-To: <6zlydkdgmowqg7cv5eeoaf7mrpnhzokyvhh5xasvznqaxnhdji@xol3jiz2lzld> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: Lws_ZfFN0E6ncHHHCKGnlhe48VJDoKIh X-Proofpoint-ORIG-GUID: Lws_ZfFN0E6ncHHHCKGnlhe48VJDoKIh X-Authority-Analysis: v=2.4 cv=Xpij+VF9 c=1 sm=1 tr=0 ts=68a56892 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=sH0VmbEyIx9rPeTW6gYA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODIwMDAxMyBTYWx0ZWRfXxFmz/Np3MHC/ jUlPdDUr92t2R5QG5TIiDfWSNnR2gJzqtqINrBGnCk8SK9Qk3X3++OmfozAwGEYrP0V7ifLdrSN CoOdYvwxXv+ivbTlsvirfxQBG10quLf01WWc4iuWH8vG8OC2QeEvzLtxk2YbGEpwdm2oAGTkpOO 9tl/Z/8i00zKokZrhMKRQw2Rr+YuwheBcXJpsvLQdm+zE8EpMo2x6ExchvHE3Os8nOXXSL+wv9d WwIxd421wC/2dsweE/UZN2WZGA/DG8NSYghGbDKibmf7AF8XYzsMKfJxMEsHsPkzYdBodFQY0hi vWUPgfaas5TPLbV+A559lcBWjZyxcnqXQXSn4DkEs67xOT1iQR17D6fRLWXnmYvhxuN0i+qc7d5 gZJ+K+mEFi0ye+LMeBAdHZjzobdN6g== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-20_02,2025-08-14_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 clxscore=1015 lowpriorityscore=0 bulkscore=0 impostorscore=0 adultscore=0 spamscore=0 phishscore=0 malwarescore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2508110000 definitions=main-2508200013 On 8/20/2025 2:43 AM, Dmitry Baryshkov wrote: > On Tue, Aug 19, 2025 at 02:52:08AM -0700, Wenbin Yao wrote: >> From: Prudhvi Yarlagadda >> >> Add support for Gen5 x4 PCIe QMP PHY found on Glymur platform. >> >> Signed-off-by: Prudhvi Yarlagadda >> Signed-off-by: Wenbin Yao >> --- >> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 29 +++++++++++++++++++++++++++++ >> 1 file changed, 29 insertions(+) >> >> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c >> index 95830dcfdec9b1f68fd55d1cc3c102985cfafcc1..e422cf6932d261074ed3419ed8806e9ed212c26c 100644 >> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c >> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c >> @@ -93,6 +93,12 @@ static const unsigned int pciephy_v6_regs_layout[QPHY_LAYOUT_SIZE] = { >> [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_POWER_DOWN_CONTROL, >> }; >> >> +static const unsigned int pciephy_v8_50_regs_layout[QPHY_LAYOUT_SIZE] = { >> + [QPHY_START_CTRL] = QPHY_V8_50_PCS_START_CONTROL, >> + [QPHY_PCS_STATUS] = QPHY_V8_50_PCS_STATUS1, >> + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V8_50_PCS_POWER_DOWN_CONTROL, >> +}; >> + >> static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = { >> QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), >> QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), >> @@ -3229,6 +3235,10 @@ static const struct qmp_pcie_offsets qmp_pcie_offsets_v6_30 = { >> .ln_shrd = 0x8000, >> }; >> >> +static const struct qmp_pcie_offsets qmp_pcie_offsets_v8_50 = { >> + .pcs = 0x9000, > Even if the driver uses only PCS regs for 8.50 currently, I'd suggest > describing the whole picture here. Otherwise it might backfire later, if > we add offsets for other blocks later and they won't match the ones used > for Glymur. OK，will add them. > >> +}; >> + >> static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { >> .lanes = 1, >> >> @@ -4258,6 +4268,22 @@ static const struct qmp_phy_cfg qmp_v6_gen4x4_pciephy_cfg = { >> .phy_status = PHYSTATUS_4_20, >> }; >> >> +static const struct qmp_phy_cfg glymur_qmp_gen5x4_pciephy_cfg = { >> + .lanes = 4, >> + >> + .offsets = &qmp_pcie_offsets_v8_50, >> + >> + .reset_list = sdm845_pciephy_reset_l, >> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), >> + .vreg_list = sm8550_qmp_phy_vreg_l, >> + .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), >> + >> + .regs = pciephy_v8_50_regs_layout, >> + >> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, >> + .phy_status = PHYSTATUS_4_20, >> +}; >> + >> static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls) >> { >> const struct qmp_phy_cfg *cfg = qmp->cfg; >> @@ -5114,6 +5140,9 @@ static const struct of_device_id qmp_pcie_of_match_table[] = { >> }, { >> .compatible = "qcom,x1p42100-qmp-gen4x4-pcie-phy", >> .data = &qmp_v6_gen4x4_pciephy_cfg, >> + }, { >> + .compatible = "qcom,glymur-qmp-gen5x4-pcie-phy", >> + .data = &glymur_qmp_gen5x4_pciephy_cfg, >> }, >> { }, >> }; >> >> -- >> 2.34.1 >> -- With best wishes Wenbin