From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 65D8A21CA03 for ; Wed, 15 Jul 2026 06:40:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784097640; cv=none; b=W5i4X18ThOmFubdKdtAEodbnJW5lUDxAhzPP77KkRmfgU487oAEnegezEyCWLI/hWm6QwRQwIJO/gEyZhlOcA0ZPC/M7UYlG5E/JsLmvOd66/jo/i98c6sR+4qM4gaxCTSeiorAE7RVCwUaDik9aK9fAro71viAsG96/jNtvFgs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784097640; c=relaxed/simple; bh=bLAfLzVt7ntqmSXbOeKwwpHZAStHJPdoa/I97we9o4U=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=sS8PnYYXjdHix+AL9YIn8bz4tvogW56RA8sNjszwMBDilLvsFSpvwBr0DhxjPeCzmmUTOFQh39gLn2Pgg8e85gV0soKYWP5GnT/AG2cYF5/oH3Vp0T8b/7u49bmkMII8y3jL2MR6jPXZlQdgLUB+yjJ/9aAXXDs+61YUjnVXb8U= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=AW1sDgyt; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="AW1sDgyt" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 54A76339; Tue, 14 Jul 2026 23:40:33 -0700 (PDT) Received: from [10.164.18.40] (unknown [10.164.18.40]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 288863F7B4; Tue, 14 Jul 2026 23:40:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784097637; bh=bLAfLzVt7ntqmSXbOeKwwpHZAStHJPdoa/I97we9o4U=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=AW1sDgytLZzTWH9K2UrxVzozwdDizwhFfha8bmtyWfqsg4w8ZklLbH8smj3Iv4tAQ vuB2FsUcRB9ML2waDsPFXZMBu4ypvQg8MR9K/tQwdn/51oyiiSzYr3WFDTVMYeYxtH hGxTRmkGoyM8GLKSPw6GY3cqIe5KWwaU5Sha44X4= Message-ID: <3360aad7-2884-4fc2-8fe9-e0ea767c9ee3@arm.com> Date: Wed, 15 Jul 2026 12:10:32 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 6/6] arm64: cpufeature: Detect BBML3 based on ID_AA64MMFR2_EL1.BBM To: Linu Cherian , Catalin Marinas , Will Deacon , Ryan Roberts , Kevin Brodsky , Suzuki K Poulose , Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20260715053408.1950475-1-linu.cherian@arm.com> <20260715053408.1950475-7-linu.cherian@arm.com> Content-Language: en-US From: Anshuman Khandual In-Reply-To: <20260715053408.1950475-7-linu.cherian@arm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 15/07/26 11:04 AM, Linu Cherian wrote: > Add ID_AA64MMFR2_EL1.BBM based BBML3 feature detection in > cpu_supports_bbml3() so that cpus with the feature would > not have to be added into MIDR based supports_bbml3_list. > > Signed-off-by: Linu Cherian Reviewed-by: Anshuman Khandual > --- > arch/arm64/kernel/cpufeature.c | 17 +++++++++-------- > 1 file changed, 9 insertions(+), 8 deletions(-) > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index 25a705e02618..b58fdcb35406 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -2133,6 +2133,12 @@ static bool hvhe_possible(const struct arm64_cpu_capabilities *entry, > > bool cpu_supports_bbml3(void) > { > + u64 mmfr2; > + > + mmfr2 = __read_sysreg_by_encoding(SYS_ID_AA64MMFR2_EL1); > + if (SYS_FIELD_GET(ID_AA64MMFR2_EL1, BBM, mmfr2) >= ID_AA64MMFR2_EL1_BBM_3) > + return true; > + > /* CPUs that support BBML3 but dont advertise through MMFR2 ID */ > static const struct midr_range supports_bbml3_list[] = { > MIDR_REV_RANGE(MIDR_CORTEX_X4, 0, 3, 0xf), > @@ -2154,15 +2160,10 @@ bool cpu_supports_bbml3(void) > {} > }; > > - if (!is_midr_in_range_list(supports_bbml3_list)) > - return false; > - > - /* > - * We currently ignore the ID_AA64MMFR2_EL1 register, and only care > - * about whether the MIDR check passes. > - */ > + if (is_midr_in_range_list(supports_bbml3_list)) > + return true; > > - return true; > + return false; > } > > static bool has_bbml3(const struct arm64_cpu_capabilities *caps, int scope)