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Fri, 05 Sep 2025 10:13:42 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 585ADgOm001637 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 5 Sep 2025 10:13:42 GMT Received: from [10.217.216.168] (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.24; Fri, 5 Sep 2025 03:13:36 -0700 Message-ID: <33610903-8dbf-4c34-b0cf-406640ff98d4@quicinc.com> Date: Fri, 5 Sep 2025 15:43:33 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V5 4/4] arm64: dts: qcom: sm8550: Add max-sd-hs-hz property Content-Language: en-US To: Konrad Dybcio , Krzysztof Kozlowski , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Adrian Hunter CC: , , , , , , , , , , References: <20250903080404.3260135-1-quic_sartgarg@quicinc.com> <20250903080404.3260135-5-quic_sartgarg@quicinc.com> <6deac56f-e21a-4447-bfa7-a414084676b8@kernel.org> <23c29fb7-c0a4-4519-9b8d-e68255b83a10@kernel.org> <18092427-3a4a-4fb2-9f75-675de98957d4@oss.qualcomm.com> From: Sarthak Garg In-Reply-To: <18092427-3a4a-4fb2-9f75-675de98957d4@oss.qualcomm.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODMwMDAxOSBTYWx0ZWRfX0+XO4CQZ3x+2 L82p59wmWOn/dgxfKJ5iiTdfedDj/0h7KJZ8F6ajbagI8W3iLJmBHn/OM/tU6csCrdPbJrLg2Cb C+i+QkVyATK3XfbzQjxuQkSsGOhhW4LsZe2HMEgUnJG+VN4aiL9q0wWsvUf8MLxhokVD81Yao8n /ttly0uubyLy1ezIpw2vZs4IG1Nd831BLpXwXpl7/MV5M5kFJIi3KYQM8hmNK2S0fviCdn0iwFo aS9PFfcBHeHNAovYrp3t4eMq8rbNl9DOYtCQ3QEYM9Mdl7Ij0dkroYqShddNaPjXZWvqYzsWGEd g/9B3kfpqv6dTYCuoyfSwoJrVNFoRxnHwMyU+N+g+3Rx5O2v0OncRw+PmlbdPt37JiB/jgAUGnj hMzJwydf X-Proofpoint-GUID: -dzS8_b23Lj0NMGLTPl02ceOtPbMOzDN X-Proofpoint-ORIG-GUID: -dzS8_b23Lj0NMGLTPl02ceOtPbMOzDN X-Authority-Analysis: v=2.4 cv=PNkP+eqC c=1 sm=1 tr=0 ts=68bab7d6 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=zTRmu9PctcSeQRTcj_MA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-05_02,2025-09-04_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 clxscore=1015 suspectscore=0 adultscore=0 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508300019 On 9/4/2025 8:20 PM, Konrad Dybcio wrote: > On 9/4/25 3:07 PM, Krzysztof Kozlowski wrote: >> On 04/09/2025 14:27, Konrad Dybcio wrote: >>> On 9/4/25 12:52 PM, Krzysztof Kozlowski wrote: >>>> On 04/09/2025 12:51, Krzysztof Kozlowski wrote: >>>>> On 04/09/2025 10:36, Konrad Dybcio wrote: >>>>>> On 9/3/25 10:21 AM, 'Krzysztof Kozlowski' via kernel wrote: >>>>>>> On 03/09/2025 10:04, Sarthak Garg wrote: >>>>>>>> Due to board-specific hardware constraints particularly related >>>>>>>> to level shifter in this case the maximum frequency for SD High-Speed >>>>>>>> (HS) mode must be limited to 37.5 MHz to ensure reliable operation of SD >>>>>>>> card in HS mode. >>>>>>>> >>>>>>>> This is achieved by introducing the `max-sd-hs-hz` property in the >>>>>>>> device tree, allowing the controller to operate within safe frequency >>>>>>>> limits for HS mode. >>>>>>>> >>>>>>> >>>>>>> Probably we will now replicate the same discussion... And it will be >>>>>>> happening every time you send the same and not reflect it in commit msg. >>>> >>>> Just to emphasize this - it will happen EVERY time. >>>> >>>>>>> >>>>>>> Bindings say board setup, this commit msg says board config, but the >>>>>>> patch says SoC. This is not correct. >>>>>> >>>>>> Both are correct, looking at the problem from two perspectives. >>>>>> >>>>>> The bindings description mentions board-specific limitations (e.g. because >>>>>> "the board's electrical design does not allow one to achieve the full rated >>>>>> frequency that the SoC can otherwise do, in a stable way") >>>>>> >>>>>> Here the author tries to argue that almost all SM8550 boards are broken >>>>>> in this sense, because the reference design did not feature the required >>>>>> passive components, making most (derivative) designs sort of "broken by >>>>>> default" - and only some (if any?) vendors decided to go with the >>>>>> additional components required to lift this limitation. >>>>>> >>>>>> This in turn makes it fair to assume the developer experience would benefit >>>>>> from having the SD card high speed modes always work (with the slight speed >>>>>> cap which may not be required for the 1 or 2 designs that took the extra >>>>>> step) without each board DT creator having to track down this property >>>>>> separately. >>>>> >>>>> And then if you send same v3, I will ask the same. Can the author >>>> >>>> v3 -> v6 >>> >>> So, would you be accepting of this patch if the commit message was: >>> >>> arm64: dts: qcom: sm8550: Limit max SD HS mode frequency by default >>> >>> Due to an implementation detail in this SoC, additional passive >>> electrical components are required to achieve the maximum rated speed >>> of the SD controller when paired with a High-Speed SD Card. Without them, >>> the clock frequency must be limited to 37.5 MHz for link stability. >>> >>> Because the reference design does not contain these components, most >>> (derivative) boards do not have them either. To accommodate for that, >>> apply the frequency limit by default and delegate lifting it to the >>> odd boards that do contain the necessary onboard hardware. >> Yes, it is an excellent explanation. > > Sarthak, if you believe what I said is accurate, feel free to copy-paste > as is > > Konrad I’ll incorporate your suggested wording in the next version of the patch to ensure it reflects the discussion accurately and avoids any confusion going forward. Appreciate your guidance! Best regards, Sarthak