From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E99E2FAC1C; Mon, 20 Oct 2025 10:04:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760954681; cv=none; b=BKs3H2VBunAAD1gJoqnvzF8dA8zlhBLtUMpM+Q9//q6Ut5R8sgrvdeeLz6KDkBP+Gs2sHOE1CR+v9+xflAJHh3LwZOBbIgRhsA3PlDc3f/UxTPLv1wPK+HtRTfHqT4bt2/rDQsFrDbxPFjicWtn4htqd/SxIg9mqFpjj0ZwJstk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760954681; c=relaxed/simple; bh=x2mWF27zYDCpuMWgQWiHXG23FvxacWyah9lAcsG8EKc=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=q6xaYXQv8rfGm80Y9SXO1qJ+ymsSB0Q0dykNWQkKVZb6nlZDKTYnCo4ve05+oFFC9hULhQUVx/YPc6HaT8sboDwPp1gytDFW3nB6y4KU4AewwxYhUU0tczUHLuMID/wwQ7EQUWU/TyfM+LM9UsY8abgAtdrzEaW+KNbYyUFqpP8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=g2rBO0NM; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="g2rBO0NM" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1760954677; bh=x2mWF27zYDCpuMWgQWiHXG23FvxacWyah9lAcsG8EKc=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=g2rBO0NMHkK12kQUBh2/MnJcHSUsh7lgw5QWOV+xgsnebkOZih6VBCXL5zzG19MLI iSNorhpODz3CLPibaT0EJ7HBGNlun+xrfOi+1sQkJO1cImEtv+329Sf9OI1+vjHZ4O OLRAy32YUeWHalsEc1F5zVmicF9CAPtqIruVKPzv2aEmMZz1593P2RXgj6ushgb1jF xK5NoGNoEY6IdFNBaByYjwhJ9Yic+oMVBGVQP0wK+t8xdHmYrRv1V6ygr0Ht6jqqpx 89HhIVA7BTRQiAvzbMQukFK0BdFqPx5VFf1c30g2CdDGPxRHL/IyvnyUFgme/ZlQOJ i6tM5ozWapRzw== Received: from [192.168.1.100] (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id B25EF17E0FAD; Mon, 20 Oct 2025 12:04:36 +0200 (CEST) Message-ID: <336e7154-b618-466c-a9b5-cc15f0f62a27@collabora.com> Date: Mon, 20 Oct 2025 12:04:36 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 07/20] mailbox: mtk-cmdq: Add mminfra_offset configuration for DRAM transaction To: Jason-JH Lin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Chun-Kuang Hu , Mauro Carvalho Chehab Cc: Matthias Brugger , Nicolas Dufresne , Nancy Lin , Singo Chang , Paul-PL Chen , Moudy Ho , Xiandong Wang , Sirius Wang , Fei Shao , Chen-yu Tsai , Project_Global_Chrome_Upstream_Group@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org References: <20251017065028.1676930-1-jason-jh.lin@mediatek.com> <20251017065028.1676930-8-jason-jh.lin@mediatek.com> From: AngeloGioacchino Del Regno Content-Language: en-US In-Reply-To: <20251017065028.1676930-8-jason-jh.lin@mediatek.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Il 17/10/25 08:44, Jason-JH Lin ha scritto: > The GCE in MT8196 is placed in MMINFRA and requires all addresses > in GCE instructions for DRAM transactions to be IOVA. > > Due to MMIO, if the GCE needs to access a hardware register at > 0x1000_0000, but the SMMU is also mapping a DRAM block at 0x1000_0000, > the MMINFRA will not know whether to write to the hardware register or > the DRAM. > To solve this, MMINFRA treats addresses greater than 2G as data paths > and those less than 2G as config paths because the DRAM start address > is currently at 2G (0x8000_0000). On the data path, MMINFRA remaps > DRAM addresses by subtracting 2G, allowing SMMU to map DRAM addresses > less than 2G. > For example, if the DRAM start address 0x8000_0000 is mapped to > IOVA=0x0, when GCE accesses IOVA=0x0, it must add a 2G offset to > the address in the GCE instruction. MMINFRA will then see it as a > data path (IOVA >= 2G) and subtract 2G, allowing GCE to access IOVA=0x0. > > Since the MMINFRA remap subtracting 2G is done in hardware and cannot > be configured by software, the address of DRAM in GCE instruction must > always add 2G to ensure proper access. After that, the shift functions > do more than just shift addresses, so the APIs were renamed to > cmdq_convert_gce_addr() and cmdq_revert_gce_addr(). > > This 2G adjustment is referred to as mminfra_offset in the CMDQ driver. > CMDQ helper can get the mminfra_offset from the cmdq_mbox_priv of > cmdq_pkt and add the mminfra_offset to the DRAM address in GCE > instructions. > > Signed-off-by: Jason-JH Lin Reviewed-by: AngeloGioacchino Del Regno