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Message-ID: <3379eac1-d398-60be-b606-10098702d7aa@arm.com>
Date:   Thu, 28 Jul 2022 17:17:08 +0100
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Subject: Re: [PATCH] perf vendor events arm64: Arm Cortex-A78C and X1C
To:     John Garry <john.garry@huawei.com>, linux-kernel@vger.kernel.org,
        linux-perf-users@vger.kernel.org, acme@kernel.org
Cc:     Will Deacon <will@kernel.org>, James Clark <james.clark@arm.com>,
        Mike Leach <mike.leach@linaro.org>,
        Leo Yan <leo.yan@linaro.org>,
        Peter Zijlstra <peterz@infradead.org>,
        Ingo Molnar <mingo@redhat.com>,
        Mark Rutland <mark.rutland@arm.com>,
        Alexander Shishkin <alexander.shishkin@linux.intel.com>,
        Jiri Olsa <jolsa@kernel.org>,
        Namhyung Kim <namhyung@kernel.org>,
        Andrew Kilroy <andrew.kilroy@arm.com>,
        linux-arm-kernel@lists.infradead.org
References: <20220610174459.615995-1-nick.forrington@arm.com>
 <2955958b-4982-42bc-7c68-82cd23462b35@huawei.com>
From:   Nick Forrington <nick.forrington@arm.com>
In-Reply-To: <2955958b-4982-42bc-7c68-82cd23462b35@huawei.com>
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On 13/06/2022 11:09, John Garry wrote:
> On 10/06/2022 18:44, Nick Forrington wrote:
>> Add PMU events for the Arm Cortex-A78C and Arm Cortex-X1C CPUs.
>>
>> Events for Arm Cortex-A78C match those for Arm Cortex-A78.
>> Events for Arm Cortex-X1C match those for Arm Cortex- X1.
>>
>> As such, this is just a mapfile change.
>>
>> Main ID Register (MIDR) and event data is sourced from the corresponding
>> Arm Technical Reference Manuals:
>>
>> Arm Cortex-A78C
>> https://developer.arm.com/documentation/102226/
>>
>> Arm Cortex-X1C
>> https://developer.arm.com/documentation/101968/
>>
>> Signed-off-by: Nick Forrington<nick.forrington@arm.com>
>
> Reviewed-by: John Garry <john.garry@huawei.com>

Could this be applied please?

Thanks,
Nick