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Fri, 05 Jun 2026 03:30:23 -0700 (PDT) Message-ID: <33989515-322d-4189-bf84-1d62a0c2d294@linaro.org> Date: Fri, 5 Jun 2026 11:30:22 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 2/2] phy: qcom-mipi-csi2: Add a CSI2 MIPI DPHY driver To: Nihal Kumar Gupta , Dmitry Baryshkov , Vijay Kumar Tumati Cc: Vladimir Zapolskiy , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Bryan O'Donoghue , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260523-x1e-csi2-phy-v8-0-a85668459521@linaro.org> <20260523-x1e-csi2-phy-v8-2-a85668459521@linaro.org> <54904b61-222d-4600-ad4c-c03a9952d337@linaro.org> <8eb709ce-3469-4303-9c3d-8d1a221cb8de@linaro.org> <59331aa7-8430-4754-861c-4ba6a4810ccd@oss.qualcomm.com> From: Bryan O'Donoghue Content-Language: en-US In-Reply-To: <59331aa7-8430-4754-861c-4ba6a4810ccd@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 05/06/2026 10:31, Nihal Kumar Gupta wrote: >> Having clock-names property doesn't mean that all values are valid. >> > CSI_COMMON_CTRL5 is a physical lane power-up bitmap: > - Bits [0,2,4,6] → D-PHY data lanes(LN0, LN2, LN4, LN6) > - Bits [1,3,5] → C-PHY trio lanes(LN1, LN3, LN5) > - Bit [7] → D-PHY clock lane(LNCK) dedicated clock enable > > In combo mode, only LN6 can be configurable as a clock lane. > > The lane-enable computation in phy_qcom_mipi_csi2_lanes_enable() uses > BIT(data[i].pos) directly, assuming physical bit positions <0 2 4 6>, > but the DT [1] uses conventional indices <0 1 2 3>, producing 0x8F > instead of the correct 0xD5. > > This goes unnoticed because the wrong value is immediately overwritten by the > hardcoded 0xD5 in lane_regs_x1e80100, making the dynamic computation effectively dead. > > Could you please fix the driver to map logical lane indices, consistent with the gen2 camss convention. > > [1]https://lore.kernel.org/all/20260326-x1e-camss-csi2-phy-dtsi- > v3-5-1d5a9306116a@linaro.org That's great, thank you for sharing this information, it moves us from "I think" to "the documentation says" --- bod