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Thu, 04 Dec 2025 08:55:48 -0800 (PST) Received: from hu-pkondeti-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7e29ff6b56esm2702035b3a.20.2025.12.04.08.55.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Dec 2025 08:55:48 -0800 (PST) Date: Thu, 4 Dec 2025 22:25:43 +0530 From: Pavan Kondeti To: Mark Rutland Cc: Pavan Kondeti , Marc Zyngier , Catalin Marinas , Will Deacon , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, rsalveti@oss.qualcomm.com Subject: Re: Alternative to arm64.nopauth cmdline for disabling Pointer Authentication Message-ID: <33ab9112-39c5-4dba-9e56-089b7e8a7243@quicinc.com> References: <3fcf6614-ee83-4a06-9024-83573b2e642e@quicinc.com> <86ecpappzi.wl-maz@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Proofpoint-ORIG-GUID: 3rIeWi2BwhPsaqqQsaTmuX4Q6y8gLEEW X-Authority-Analysis: v=2.4 cv=Rv/I7SmK c=1 sm=1 tr=0 ts=6931bd15 cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=kj9zAlcOel0A:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=Hg61_yuSoULxYLHEoxwA:9 a=CjuIK1q_8ugA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-GUID: 3rIeWi2BwhPsaqqQsaTmuX4Q6y8gLEEW X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjA0MDEzNiBTYWx0ZWRfXx1LBPfTpYc4X VORxB/eyJQsmHZT1D+f/eN5OpxKT/9f1CZEWEYVyvIyYgIqI/LafBOoVQoCLAd3IPCm9so2R5KJ aZrU4iqkxd8mlj7Sx8KFP5kVwj5w2Rw5XiK03yD0iS/dRONwdSVBZq6BFXfb03WvwNvdhy+QMs3 henBizFXt1HLuioUoZGgEoRfqtYWFrKLtGQMEI6sTQGYULljttT9AxOaES8as9l+DFsWcT/jJNT 3XgyuvS9FGfgSwB7Blj6Rlk4xPp/CBLYZZXyzTkvfN4+/AKE/m4v8j/ziwBxp/70MJzUM0JqavA mqwxL02fdaZkpQQJBeloCYOpAkhKomCny1mgHPOK3AKusrlO3nr0arwR/W7Ha+iWMO/3NJGshzE 2LIHTZP6zveZXsNAu9bN4g/NrZslkg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-04_04,2025-12-04_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 spamscore=0 adultscore=0 impostorscore=0 clxscore=1015 suspectscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512040136 On Thu, Dec 04, 2025 at 12:04:42PM +0000, Mark Rutland wrote: > Hi Pavan, Marc, > > On Thu, Dec 04, 2025 at 04:06:12PM +0530, Pavan Kondeti wrote: > > On Thu, Dec 04, 2025 at 09:15:29AM +0000, Marc Zyngier wrote: > > > On Thu, 04 Dec 2025 04:07:15 +0000, > > > Pavan Kondeti wrote: > > > > Hi > > > > > > > > The pointer authentication feature (PAuth) is only supported on > > > > 0-3 CPUs but it is not supported on 4-7 CPUS on QCS8300. > > > > On what grounds? Hardware incompatibility? I seriously doubt it, > > > since nobody glues pre-8.3 CPUs to anything more modern. > > Marc, it seems like that's exactly that's happened here. :/ > > > I see that Linux runs at EL2 and AA64ISAR1 register values on CPU#0 > > (A78) indicates that PAuth is supported but not for CPU#4 (A55). I am > > told, there are no other controls outside EL2 (trap) to manipulate > > this feature. So, I am assuming that this is indeed reflecting the HW. > > Cortex-A78 doesn't have pointer authentication, but Cortex-A78C does, so > maybe you actually have Cortex-A78C? > > What are the MIDRs on this SoC? e.g. the output of: > > cat /sys/devices/system/cpu/cpu*/regs/identification/midr_el1 | sort | uniq > > If this SoC has both Cortex-A78C and Cortex-A55, that's a rather > unfortunate combination that should have been caught at the SoC design > phase, as Marc alluded to. Yes. The MIDR register indicate the same. A78C + A55 root@v8a-arm64:~# cat /sys/devices/system/cpu/cpu*/regs/identification/midr_el1 0x00000000410fd4b2 0x00000000410fd4b2 0x00000000410fd4b2 0x00000000410fd4b2 0x00000000412fd050 0x00000000412fd050 0x00000000412fd050 0x00000000412fd050 > > [...] > > > > > This patch [2] from Catalin adds a devicetree property under memory {} > > > > to disable MTE. > > Catalin's patch was a bit different. It described whether the memory > range supported tags (and was actually a property of the memory). That > patch didn't make it into mainline AFAICT. > > [...] > > > I understand that this does not fall under errata but is > > there a possiblity to introduce an Errata targeting CPU#0 MIDR and > > disabling the Pointer authentication? I understand that if there is > > another Qualcomm SoC that exists with all CPUs supporting pointer > > authentication with same MIDR, we may be disabling the feature but this > > is something I can check internally. > > I strongly suspect we cannot use the MIDR for this. Per: > > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=53a52a0ec7680287b170b36488203b5822e6da2d > > ... Qualcomm's Kryo {Prime,Gold,Silver} parts seem to identify > themselves as Arm ltd implementations, and those will appear in other > non-Qualcomm SoCs. Thank you for explaining this. Agree that we can't use MIDR based workaround here. > > Without know *exactly* which MIDRs you have on this part, we cannot say. > > Regardless, I strongly suspect that we have to live with the command > line option for these parts. > Got it. Thanks, Pavan