From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EAB44C04EB9 for ; Mon, 3 Dec 2018 08:51:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B6FEB2145D for ; Mon, 3 Dec 2018 08:51:21 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B6FEB2145D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725967AbeLCIvY (ORCPT ); Mon, 3 Dec 2018 03:51:24 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:16071 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1725849AbeLCIvY (ORCPT ); Mon, 3 Dec 2018 03:51:24 -0500 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 8BADBCDDD6660; Mon, 3 Dec 2018 16:51:15 +0800 (CST) Received: from [127.0.0.1] (10.142.63.192) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.408.0; Mon, 3 Dec 2018 16:51:10 +0800 CC: , , , Greg Kroah-Hartman , "Rob Herring" , Mark Rutland , "John Stultz" Subject: Re: [PATCH v1 01/12] dt-bindings: usb: add support for dwc3 controller on HiSilicon SoCs To: Sergei Shtylyov , , , References: <20181203034515.91412-1-chenyu56@huawei.com> <20181203034515.91412-2-chenyu56@huawei.com> From: Chen Yu Message-ID: <33cda716-d09c-28e7-d4b4-26f246786f5e@huawei.com> Date: Mon, 3 Dec 2018 16:51:09 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.5.2 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 8bit X-Originating-IP: [10.142.63.192] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 2018/12/3 16:35, Sergei Shtylyov wrote: > Hello! > > On 03.12.2018 6:45, Yu Chen wrote: > >> This patch adds binding descriptions to support the dwc3 controller >> on HiSilicon SoCs and boards like the HiKey960. >> >> Cc: Greg Kroah-Hartman >> Cc: Rob Herring >> Cc: Mark Rutland >> Cc: John Stultz >> Signed-off-by: Yu Chen >> --- >>   .../devicetree/bindings/usb/dwc3-hisi.txt          | 67 ++++++++++++++++++++++ >>   1 file changed, 67 insertions(+) >>   create mode 100644 Documentation/devicetree/bindings/usb/dwc3-hisi.txt >> >> diff --git a/Documentation/devicetree/bindings/usb/dwc3-hisi.txt b/Documentation/devicetree/bindings/usb/dwc3-hisi.txt >> new file mode 100644 >> index 000000000000..d32d2299a0a1 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/usb/dwc3-hisi.txt >> @@ -0,0 +1,67 @@ >> +HiSilicon DWC3 USB SoC controller >> + >> +This file documents the parameters for the dwc3-hisi driver. >> + >> +Required properties: >> +- compatible:    should be "hisilicon,hi3660-dwc3" >> +- clocks:    A list of phandle + clock-specifier pairs for the >> +        clocks listed in clock-names >> +- clock-names:    Specify clock names >> +- resets:    list of phandle and reset specifier pairs. >> + >> +Sub-nodes: >> +The dwc3 core should be added as subnode to HiSilicon DWC3 as shown in the >> +example below. The DT binding details of dwc3 can be found in: >> +Documentation/devicetree/bindings/usb/dwc3.txt >> + >> +Example: >> +    usb3: hisi_dwc3 { >> +        compatible = "hisilicon,hi3660-dwc3"; >> +        #address-cells = <2>; >> +        #size-cells = <2>; >> +        ranges; >> + >> +        clocks = <&crg_ctrl HI3660_CLK_ABB_USB>, >> +             <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>; >> +        clock-names = "clk_usb3phy_ref", "aclk_usb3otg"; >> +        assigned-clocks = <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>; >> +        assigned-clock-rates = <229000000>; >> +        resets = <&crg_rst 0x90 8>, >> +             <&crg_rst 0x90 7>, >> +             <&crg_rst 0x90 6>, >> +             <&crg_rst 0x90 5>; >> + >> +        dwc3: dwc3@ff100000 { > >     According to the DT spec, the node names should be generic, not chip specific, i.e. usb@ff100000 in this case. > Do you mean it should be usb@ff100000: dwc3@ff100000 ? Thanks! > [...] > > MBR, Sergei > > . >