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([2a01:e0a:3d9:2080:d283:7a7e:4c57:678d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-432bd0e16f4sm21785092f8f.11.2026.01.09.00.31.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Jan 2026 00:31:13 -0800 (PST) Message-ID: <34590271-0e34-45cd-ac6f-6f901e833087@linaro.org> Date: Fri, 9 Jan 2026 09:31:12 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Reply-To: Neil Armstrong Subject: Re: [PATCH v3 0/3] Retrieve information about DDR from SMEM To: Konrad Dybcio , Bjorn Andersson , Kees Cook , "Gustavo A. R. Silva" , Rob Clark , Sean Paul , Akhil P Oommen , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio References: <20260108-topic-smem_dramc-v3-0-6b64df58a017@oss.qualcomm.com> From: Neil Armstrong Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: <20260108-topic-smem_dramc-v3-0-6b64df58a017@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 1/8/26 15:21, Konrad Dybcio wrote: > SMEM allows the OS to retrieve information about the DDR memory. > Among that information, is a semi-magic value called 'HBB', or Highest > Bank address Bit, which multimedia drivers (for hardware like Adreno > and MDSS) must retrieve in order to program the IP blocks correctly. > > This series introduces an API to retrieve that value, uses it in the > aforementioned programming sequences and exposes available DDR > frequencies in debugfs (to e.g. pass to aoss_qmp debugfs). More > information can be exposed in the future, as needed. > > Patch 3 should really be merged after 1&2 > > Signed-off-by: Konrad Dybcio > --- > Changes in v3: > - Support v6 and v7 DDRInfo (v7 is used on e.g. Hamoa) > - Handle rare cases of DDRInfo v5 with additional trailing data > - Rebase/adjust to SSoT UBWC > - Expose hbb value in debugfs > - cosmetic changes > - Link to v2: https://lore.kernel.org/r/20250410-topic-smem_dramc-v2-0-dead15264714@oss.qualcomm.com > > Changes in v2: > - Avoid checking for < 0 on unsigned types > - Overwrite Adreno UBWC data to keep the data shared with userspace > coherent with what's programmed into the hardware > - Call get_hbb() in msm_mdss_enable() instead of all UBWC setup > branches separately > - Pick up Bjorn's rb on patch 1 > - Link to v1: https://lore.kernel.org/r/20250409-topic-smem_dramc-v1-0-94d505cd5593@oss.qualcomm.com > > --- > Konrad Dybcio (3): > soc: qcom: smem: Expose DDR data from SMEM > soc: qcom: ubwc: Get HBB from SMEM > drm/msm/adreno: Trust the SSoT UBWC config > > drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 11 +- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 82 +------ > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 - > drivers/soc/qcom/Makefile | 3 +- > drivers/soc/qcom/smem.c | 14 +- > drivers/soc/qcom/smem.h | 9 + > drivers/soc/qcom/smem_dramc.c | 408 ++++++++++++++++++++++++++++++++ > drivers/soc/qcom/ubwc_config.c | 69 ++++-- > include/linux/soc/qcom/smem.h | 4 + > 9 files changed, 485 insertions(+), 120 deletions(-) > --- > base-commit: fc4e91c639c0af93d63c3d5bc0ee45515dd7504a > change-id: 20250409-topic-smem_dramc-6467187ac865 > > Best regards, Tested-by: Neil Armstrong # on SM8650-HDK root@qemuarm64:~# cat /sys/kernel/debug/qcom_smem/ dram_frequencies hbb root@qemuarm64:~# cat /sys/kernel/debug/qcom_smem/dram_frequencies 200000000 547200000 768000000 1555200000 1708800000 2092800000 2736000000 3187200000 3686400000 4224000000 root@qemuarm64:~# cat /sys/kernel/debug/qcom_smem/hbb 16 Thanks, Neil