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charset=UTF-8 Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: 46B752199A X-Spam-Score: -3.00 X-Spam-Level: X-Spam-Flag: NO X-Spamd-Result: default: False [-3.00 / 50.00]; BAYES_HAM(-3.00)[100.00%]; SUSPICIOUS_RECIPS(1.50)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; NEURAL_HAM_SHORT(-0.20)[-1.000]; R_DKIM_ALLOW(-0.20)[suse.de:s=susede2_rsa,suse.de:s=susede2_ed25519]; MIME_GOOD(-0.10)[text/plain]; MX_GOOD(-0.01)[]; XM_UA_NO_VERSION(0.01)[]; TO_MATCH_ENVRCPT_ALL(0.00)[]; FUZZY_BLOCKED(0.00)[rspamd.com]; RBL_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[2a07:de40:b281:104:10:150:64:97:from]; RCPT_COUNT_TWELVE(0.00)[21]; DKIM_SIGNED(0.00)[suse.de:s=susede2_rsa,suse.de:s=susede2_ed25519]; MIME_TRACE(0.00)[0:+]; ARC_NA(0.00)[]; FREEMAIL_ENVRCPT(0.00)[gmail.com]; FREEMAIL_CC(0.00)[linutronix.de,kernel.org,gmail.com,google.com,linux.com,pengutronix.de,suse.com,raspberrypi.com]; RCVD_TLS_ALL(0.00)[]; SPAMHAUS_XBL(0.00)[2a07:de40:b281:104:10:150:64:97:from]; RCVD_COUNT_TWO(0.00)[2]; FROM_EQ_ENVFROM(0.00)[]; FROM_HAS_DN(0.00)[]; TO_DN_SOME(0.00)[]; MID_RHS_MATCH_FROM(0.00)[]; TAGGED_RCPT(0.00)[dt]; RECEIVED_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[2a07:de40:b281:106:10:150:64:167:received]; DKIM_TRACE(0.00)[suse.de:+]; RCVD_VIA_SMTP_AUTH(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:helo,imap1.dmz-prg2.suse.org:rdns,suse.de:dkim] X-Rspamd-Action: no action X-Rspamd-Server: rspamd1.dmz-prg2.suse.org Hi Florian, On 6/26/24 14:31, Florian Fainelli wrote: > Hi, > > On 26/06/2024 11:45, Stanimir Varbanov wrote: >> This patchset aims to add bare minimum support for bcm2712 >> in brcmstb PCIe driver needed to support the peripherals from >> RP1 south-bridge found in RPi5. In order to support RP1 >> PCIe endpoint peripherals a new interrupt controller is added. >> The interrupt controller supports 64 interrupt sources which >> are enough to handle 61 RP1 peripherals. >> >> Patch 1 is adding DT binding schema for the MIP interrupt >> controller, patch 2 is adding relevant changes for PCIe >> bcm2712 in yaml. Patch 3 adds MIP intterrupt cotroller driver. >> Patches 4 and 5 are preparations for adding bcm2712 support in 6. >> The last patch updates bcm2712 .dsti by adding pcie DT nodes. >> >> Few concerns about the implementation: >>   - the connection between MIP interrupt-controller and PCIe RC is >>     done through BAR1. The PCIe driver is parsing the msi_parent >>     DT property in order to obtain few private DT properties like >>     "brcm,msi-pci-addr" and "reg". IMO this looks hackish but I failed >>     to find something better. Ideas? >> >>   - in downstream RPi kernel "ranges" and "dma-ranges" DT properties >>     are under an axi {} simple-bus node even that PCIe block is on CPU >>     MMIO bus. I tried to merge axi {} in soc {} and the result could be >>     seen on the last patch in this series, but I'm still not sure that >>     it looks good enough. >> >> This series has been functionally tested on OpenSUSE Tumbleweed with >> downstream RP1 south-bridge PCIe endpoint driver implementation as >> MFD by using ethernet which is part of it. >> >> The series is based on Andrea's "Add minimal boot support for >> Raspberry Pi 5" >> series. >> >> Comments are welcome! > > We are just about submitting support for 7712 which is the sister chip > of 2712 and requires similar, if not identical types of changes to > pcie-brcmstb.c, would you mind reviewing that patch series when it gets > posted by Jim in the next few days, and base yours upon that one? It Sure, I'll review bcm7712 series and rebase bcm2712 on top of it. > does separate changes in a more atomic and a more reviewer friendly > rather than having one big commit modifying pcie-brcmstb.c Agreed. > > Thanks. ~Stan