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I want to explore what= page size >>>> means. >>>> >>>> The kernel uses the same value - PAGE_SIZE - for two things: >>>> >>>> - the order-0 buddy allocation size; >>>> >>>> - the granularity of virtual address space mapping; >>>> >>>> I think we can benefit from separating these two meanings and allowi= ng >>>> order-0 allocations to be larger than the virtual address space cove= red by a >>>> PTE entry. >>>> >>>> The main motivation is scalability. Managing memory on multi-terabyt= e >>>> machines in 4k is suboptimal, to say the least. >>>> >>>> Potential benefits of the approach (assuming 64k pages): >>>> >>>> - The order-0 page size cuts struct page overhead by a factor of= 16. From >>>> ~1.6% of RAM to ~0.1%; >>>> >>>> - TLB wins on machines with TLB coalescing as long as mapping is= naturally >>>> aligned; >>>> >>>> - Order-5 allocation is 2M, resulting in less pressure on the zo= ne lock; >>>> >>>> - 1G pages are within possibility for the buddy allocator - orde= r-14 >>>> allocation. It can open the road to 1G THPs. >>>> >>>> - As with THP, fewer pages - less pressure on the LRU lock; >>>> >>>> - ... >>>> >>>> The trade-off is memory waste (similar to what we have on architectu= res with >>>> native 64k pages today) and complexity, mostly in the core-MM code. >>>> >>>> =3D=3D Design considerations =3D=3D >>>> >>>> I want to split PAGE_SIZE into two distinct values: >>>> >>>> - PTE_SIZE defines the virtual address space granularity; >>>> >>>> - PG_SIZE defines the size of the order-0 buddy allocation; >>>> >>>> PAGE_SIZE is only defined if PTE_SIZE =3D=3D PG_SIZE. It will flag w= hich code >>>> requires conversion, and keep existing code working while conversion= is in >>>> progress. >>>> >>>> The same split happens for other page-related macros: mask, shift, >>>> alignment helpers, etc. >>>> >>>> PFNs are in PTE_SIZE units. >>>> >>>> The buddy allocator and page cache (as well as all I/O) operate in P= G_SIZE >>>> units. >>>> >>>> Userspace mappings are maintained with PTE_SIZE granularity. No ABI = changes >>>> for userspace. But we might want to communicate PG_SIZE to userspace= to >>>> get the optimal results for userspace that cares. >>>> >>>> PTE_SIZE granularity requires a substantial rework of page fault and= VMA >>>> handling: >>>> >>>> - A struct page pointer and pgprot_t are not enough to create a = PTE entry. >>>> We also need the offset within the page we are creating the PT= E for. >>>> >>>> - Since the VMA start can be aligned arbitrarily with respect to= the >>>> underlying page, vma->vm_pgoff has to be changed to vma->vm_pt= eoff, >>>> which is in PTE_SIZE units. >>>> >>>> - The page fault handler needs to handle PTE_SIZE < PG_SIZE, inc= luding >>>> misaligned cases; >>>> >>>> Page faults into file mappings are relatively simple to handle as we= >>>> always have the page cache to refer to. So you can map only the part= of the >>>> page that fits in the page table, similarly to fault-around. >>>> >>>> Anonymous and file-CoW faults should also be simple as long as the V= MA is >>>> aligned to PG_SIZE in both the virtual address space and with respec= t to >>>> vm_pgoff. We might waste some memory on the ends of the VMA, but it = is >>>> tolerable. >>>> >>>> Misaligned anonymous and file-CoW faults are a pain. Specifically, m= apping >>>> pages across a page table boundary. In the worst case, a page is map= ped across >>>> a PGD entry boundary and PTEs for the page have to be put in two sep= arate >>>> subtrees of page tables. >>>> >>>> A naive implementation would map different pages on different sides = of a >>>> page table boundary and accept the waste of one page per page table = crossing. >>>> The hope is that misaligned mappings are rare, but this is suboptima= l. >>>> >>>> mremap(2) is the ultimate stress test for the design. >>>> >>>> On x86, page tables are allocated from the buddy allocator and if PG= _SIZE >>>> is greater than 4 KB, we need a way to pack multiple page tables int= o a >>>> single page. We could use the slab allocator for this, but it would >>>> require relocating the page-table metadata out of struct page. >>> >>> When discussing per-process page sizes with Ryan and Dev, I mentioned= that >>> having a larger emulated page size could be interesting for other >>> architectures as well. >>> >>> That is, we would emulate a 64K page size on Intel for user space as = well, >>> but let the OS work with 4K pages. >>> >>> We'd only allocate+map large folios into user space + pagecache, but = still >>> allow for page tables etc. to not waste memory. >>> >>> So "most" of your allocations in the system would actually be at leas= t 64k, >>> reducing zone lock contention etc. >> >> I am not convinced emulation would help zone lock contention. I expect= >> contention to be higher if page allocator would see a mix of 4k and 64= k >> requests. It sounds like constant split/merge under the lock. > > If most your allocations are larger, then there isn't that much splitti= ng/merging. > > There will be some for the < 64k allocations of course, but when all us= er space+page cache is >=3D 64 then the split/merge + zone lock should be= heavily reduced. > >> >>> It doesn't solve all the problems you wanted to tackle on your list (= e.g., >>> "struct page" overhead, which will be sorted out by memdescs). >> >> I don't think we can serve 1G pages out of buddy allocator with 4k >> order-0. And without it, I don't see how to get to a viable 1G THPs. > > Zi Yan was one working on this, and I think we had ideas on how to make= that work in the long run. Right. The idea is to add super pageblock (or whatever name), which consi= sts of N consecutive pageblocks, so that anti fragmentation can work at larger granularity, e.= g., 1GB, to create free pages. Whether 1GB free pages from memory compaction need to go into= buddy allocator or not is debatable. -- Best Regards, Yan, Zi