From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8BA0C2EDD78 for ; Wed, 18 Feb 2026 21:44:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.7 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771451079; cv=none; b=HeNEAWAzasHcEWCObhEh7Sj70FTyiQWJTYNVITsH05OvpgD8zpuJMyeZGrELvMRxK70sKAn216Eom1hyvzwHOF2u6B+8rEMxo97GG2DAt9yts8EeqrLc8BOt6VPa8c/B4qm3nvcrv2efz0fh1yDG6+ntbVN7fVFwpjan+/POLqU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771451079; c=relaxed/simple; bh=Q/NM4+L4s74SDQPnXlQrOIbmTPFRd1k9oHVDV0GopWk=; h=Message-ID:Subject:From:To:Cc:Date:In-Reply-To:References: Content-Type:MIME-Version; b=Lc2sIynlfUxVECLz4wWUntMoSC8Dsgx6L8U4tHY86aX1wUBRM8KSE0pJhIwUeJNDWzev8+XaQznPaT3xt32klbpzFqQ/99DHh77l0PHaqP4RLCc+SN++B7rcYWL8xxK3ve3DzZPcqJQZH5blev0KSc1nBiJNlg55+vo8lgcZaVY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=W+2LQvme; arc=none smtp.client-ip=192.198.163.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="W+2LQvme" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1771451078; x=1802987078; h=message-id:subject:from:to:cc:date:in-reply-to: references:content-transfer-encoding:mime-version; bh=Q/NM4+L4s74SDQPnXlQrOIbmTPFRd1k9oHVDV0GopWk=; b=W+2LQvmeyY/0yUbNZT9pTQLn6ksEwp0GOQ0ViRNc9pX6gHU9lNjSFm1U DmW+uUtw3DJPrPXmXkc/jdIt7UTEgGJ9jWJY9yBqVSaKasSaN4lc4YlGM 9/gtUk+rr2jUhAsutpXL/OqgTDZLaYV83QiL3Eh8cdf4bdBfaLAikIFUx 2aMZ8mWGxQBwKf0naJNL/MHwZYHIx7pbiDAVSr9MkvCu2XG1eFQGkeEGm C2nmv0JT1j4fE0lBQ/3JG0WqLyZGlaqAbVvleVMac0hNDG3T5/czYAfi/ nOV188fPl9VsM5qGt8c01TEAgy2dqOwt42eFL2BhEXwr4UlyLB77SUw5w w==; X-CSE-ConnectionGUID: pHwab7QATgKV9RbOEspP1Q== X-CSE-MsgGUID: xAUTqW4DRXugk/V/oacHSw== X-IronPort-AV: E=McAfee;i="6800,10657,11705"; a="97996615" X-IronPort-AV: E=Sophos;i="6.21,299,1763452800"; d="scan'208";a="97996615" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Feb 2026 13:44:37 -0800 X-CSE-ConnectionGUID: 7KXq+m/SQHCgnaIfGM2qvw== X-CSE-MsgGUID: aPoToGNsSfWTghDtov13pw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,299,1763452800"; d="scan'208";a="252010570" Received: from unknown (HELO [10.241.243.83]) ([10.241.243.83]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Feb 2026 13:44:37 -0800 Message-ID: <34817728117f513084f39a99e18ea9a18cbfd3ae.camel@linux.intel.com> Subject: Re: [PATCH v3 15/21] sched/cache: Disable cache aware scheduling for processes with high thread counts From: Tim Chen To: Madadi Vineeth Reddy Cc: Peter Zijlstra , Ingo Molnar , K Prateek Nayak , "Gautham R . Shenoy" , Vincent Guittot , Chen Yu , Juri Lelli , Dietmar Eggemann , Steven Rostedt , Ben Segall , Mel Gorman , Valentin Schneider , Hillf Danton , Shrikanth Hegde , Jianyong Wu , Yangyu Chen , Tingyin Duan , Vern Hao , Vern Hao , Len Brown , Aubrey Li , Zhao Liu , Chen Yu , Adam Li , Aaron Lu , Tim Chen , Josh Don , Gavin Guo , Qais Yousef , Libo Chen , linux-kernel@vger.kernel.org Date: Wed, 18 Feb 2026 13:44:36 -0800 In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.58.1 (3.58.1-1.fc43) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Wed, 2026-02-18 at 23:24 +0530, Madadi Vineeth Reddy wrote: > On 11/02/26 03:48, Tim Chen wrote: > > From: Chen Yu > >=20 > >=20 [ .. snip ..] > > =20 > > diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c > > index d1145997b88d..86b6b08e7e1e 100644 > > --- a/kernel/sched/fair.c > > +++ b/kernel/sched/fair.c > > @@ -1223,6 +1223,19 @@ static inline bool valid_llc_buf(struct sched_do= main *sd, > > return valid_llc_id(id); > > } > > =20 > > +static bool exceed_llc_nr(struct mm_struct *mm, int cpu) > > +{ > > + int smt_nr =3D 1; > > + > > +#ifdef CONFIG_SCHED_SMT > > + if (sched_smt_active()) > > + smt_nr =3D cpumask_weight(cpu_smt_mask(cpu)); > > +#endif > > + > > + return !fits_capacity((mm->sc_stat.nr_running_avg * smt_nr), > > + per_cpu(sd_llc_size, cpu)); >=20 >=20 > On Power10/Power11 with SMT4 and LLC size of 4, this check > effectively disables cache-aware scheduling for any process. There are 4 cores per LLC, with 4 SMT per core? In that case, once we have = more than 4 running threads and there's another idle LLC available, seems like putting the additional thread on a different LLC is the right thing to do as threads sharing a core will usually be much slower. But when number of threads are under 4, we should still be doing aggregation. Perhaps I am misunderstanding your topology. Tim >=20 > I raised this point in v1 as well. Increasing the threshold > doesn't seem like a viable solution either, as that would regress > hackbench/ebizzy. >=20 > Is there a way to make this useful for architectures with small LLC > sizes? One possible approach we were exploring is to have LLC at a > hemisphere level that comprise multiple SMT4 cores. >=20 > Thanks, > Vineeth