From: Jon Hunter <jonathanh@nvidia.com>
To: webgeek1234@gmail.com, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Thierry Reding <thierry.reding@gmail.com>
Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] arm64: tegra: Enable NVDEC and NVENC on Tegra210
Date: Wed, 29 Oct 2025 09:55:25 +0000 [thread overview]
Message-ID: <34d86deb-1087-4112-ba7d-bbc0cc542635@nvidia.com> (raw)
In-Reply-To: <20250816-tegra210-media-enable-v1-1-bdb1c2554f0d@gmail.com>
On 16/08/2025 07:03, Aaron Kling via B4 Relay wrote:
> From: Aaron Kling <webgeek1234@gmail.com>
>
> The other engines are already enabled, finish filling out the media
> engine nodes and power domains.
>
> Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
> ---
> arch/arm64/boot/dts/nvidia/tegra210.dtsi | 28 ++++++++++++++++++++++++++--
> 1 file changed, 26 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
> index 402b0ede1472af625d9d9e811f5af306d436cc98..80d7571d0350205b080bcf48b8b8e2c1b93227f2 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
> @@ -277,13 +277,25 @@ dsib: dsi@54400000 {
> nvdec@54480000 {
> compatible = "nvidia,tegra210-nvdec";
> reg = <0x0 0x54480000 0x0 0x00040000>;
> - status = "disabled";
> + clocks = <&tegra_car TEGRA210_CLK_NVDEC>;
> + clock-names = "nvdec";
> + resets = <&tegra_car 194>;
> + reset-names = "nvdec";
> +
> + iommus = <&mc TEGRA_SWGROUP_NVDEC>;
> + power-domains = <&pd_nvdec>;
> };
>
> nvenc@544c0000 {
> compatible = "nvidia,tegra210-nvenc";
> reg = <0x0 0x544c0000 0x0 0x00040000>;
> - status = "disabled";
> + clocks = <&tegra_car TEGRA210_CLK_NVENC>;
> + clock-names = "nvenc";
> + resets = <&tegra_car 219>;
> + reset-names = "nvenc";
> +
> + iommus = <&mc TEGRA_SWGROUP_NVENC>;
> + power-domains = <&pd_nvenc>;
> };
>
> tsec@54500000 {
> @@ -894,6 +906,18 @@ pd_audio: aud {
> #power-domain-cells = <0>;
> };
>
> + pd_nvenc: mpe {
> + clocks = <&tegra_car TEGRA210_CLK_NVENC>;
> + resets = <&tegra_car 219>;
> + #power-domain-cells = <0>;
> + };
> +
> + pd_nvdec: nvdec {
> + clocks = <&tegra_car TEGRA210_CLK_NVDEC>;
> + resets = <&tegra_car 194>;
> + #power-domain-cells = <0>;
> + };
> +
> pd_sor: sor {
> clocks = <&tegra_car TEGRA210_CLK_SOR0>,
> <&tegra_car TEGRA210_CLK_SOR1>,
>
Looks good to me!
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Jon
--
nvpublic
next prev parent reply other threads:[~2025-10-29 9:55 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-16 6:03 Aaron Kling via B4 Relay
2025-10-20 19:35 ` Aaron Kling
2025-10-29 9:55 ` Jon Hunter [this message]
2025-10-29 13:39 ` Diogo Ivo
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