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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab6e47cf9desm769517966b.55.2025.02.03.05.29.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 03 Feb 2025 05:29:40 -0800 (PST) Message-ID: <34dd8cbb-3e1c-4c8f-93ef-43b041804877@oss.qualcomm.com> Date: Mon, 3 Feb 2025 14:29:38 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 1/4] arm64: dts: qcom: sm8650: drop cpu thermal passive trip points To: Neil Armstrong , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250203-topic-sm8650-thermal-cpu-idle-v4-0-65e35f307301@linaro.org> <20250203-topic-sm8650-thermal-cpu-idle-v4-1-65e35f307301@linaro.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250203-topic-sm8650-thermal-cpu-idle-v4-1-65e35f307301@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: IwgZHr6mn4WWqdLbnZivXalUXMcgPrNH X-Proofpoint-ORIG-GUID: IwgZHr6mn4WWqdLbnZivXalUXMcgPrNH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-03_05,2025-01-31_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 spamscore=0 malwarescore=0 priorityscore=1501 suspectscore=0 adultscore=0 clxscore=1015 impostorscore=0 mlxscore=0 lowpriorityscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502030099 On 3.02.2025 2:23 PM, Neil Armstrong wrote: > On the SM8650, the dynamic clock and voltage scaling (DCVS) is done in an > hardware controlled loop using the LMH and EPSS blocks with constraints and > OPPs programmed in the board firmware. > > Since the Hardware does a better job at maintaining the CPUs temperature > in an acceptable range by taking in account more parameters like the die > characteristics or other factory fused values, it makes no sense to try > and reproduce a similar set of constraints with the Linux cpufreq thermal > core. > > In addition, the tsens IP is responsible for monitoring the temperature > across the SoC and the current settings will heavily trigger the tsens > UP/LOW interrupts if the CPU temperatures reaches the hardware thermal > constraints which are currently defined in the DT. And since the CPUs > are not hooked in the thermal trip points, the potential interrupts and > calculations are a waste of system resources. > > Drop the current passive trip points and only leave the critical trip > point that will trigger a software system reboot before an hardware > thermal shutdown in the allmost impossible case the hardware DCVS cannot > handle the temperature surge. > > Signed-off-by: Neil Armstrong > --- Reviewed-by: Konrad Dybcio Konrad