From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6BCBCCA473 for ; Fri, 1 Jul 2022 02:34:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233613AbiGACeS (ORCPT ); Thu, 30 Jun 2022 22:34:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60354 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233809AbiGACeI (ORCPT ); Thu, 30 Jun 2022 22:34:08 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E776061D72; Thu, 30 Jun 2022 19:34:05 -0700 (PDT) X-UUID: f40ea92af97b471d979a7fb212005239-20220701 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.7,REQID:763fb36e-1995-4133-96ee-2db78727ceb8,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:87442a2,CLOUDID:021c3f86-57f0-47ca-ba27-fe8c57fbf305,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: f40ea92af97b471d979a7fb212005239-20220701 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 771503672; Fri, 01 Jul 2022 10:34:02 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 1 Jul 2022 10:34:00 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 1 Jul 2022 10:33:59 +0800 Message-ID: <34ecaadd5aac5275fc475c9f01afaabfa15aa542.camel@mediatek.com> Subject: Re: [PATCH v12 05/10] drm/mediatek: Add MT8195 Embedded DisplayPort driver From: Rex-BC Chen To: CK Hu , "chunkuang.hu@kernel.org" , "p.zabel@pengutronix.de" , "daniel@ffwll.ch" , "robh+dt@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "mripard@kernel.org" , "tzimmermann@suse.de" , "matthias.bgg@gmail.com" , "deller@gmx.de" , "airlied@linux.ie" CC: "msp@baylibre.com" , "granquet@baylibre.com" , Jitao Shi =?UTF-8?Q?=28=E7=9F=B3=E8=AE=B0=E6=B6=9B=29?= , "wenst@chromium.org" , "angelogioacchino.delregno@collabora.com" , "dri-devel@lists.freedesktop.org" , "linux-mediatek@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-fbdev@vger.kernel.org" , Project_Global_Chrome_Upstream_Group Date: Fri, 1 Jul 2022 10:33:58 +0800 In-Reply-To: <599af6f875cb85bab1a6f0e03bbfb74a2a3b948c.camel@mediatek.com> References: <20220627080341.5087-1-rex-bc.chen@mediatek.com> <20220627080341.5087-6-rex-bc.chen@mediatek.com> <599af6f875cb85bab1a6f0e03bbfb74a2a3b948c.camel@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 2022-06-30 at 09:47 +0800, CK Hu wrote: > Hi, Bo-Chen: > > On Mon, 2022-06-27 at 16:03 +0800, Bo-Chen Chen wrote: > > From: Markus Schneider-Pargmann > > > > This patch adds a embedded displayport driver for the MediaTek > > mt8195 > > SoC. > > > > It supports the MT8195, the embedded DisplayPort units. It offers > > DisplayPort 1.4 with up to 4 lanes. > > > > The driver creates a child device for the phy. The child device > > will > > never exist without the parent being active. As they are sharing a > > register range, the parent passes a regmap pointer to the child so > > that > > both can work with the same register range. The phy driver sets > > device > > data that is read by the parent to get the phy device that can be > > used > > to control the phy properties. > > > > This driver is based on an initial version by > > Jitao shi > > > > Signed-off-by: Markus Schneider-Pargmann > > Signed-off-by: Guillaume Ranquet > > [Bo-Chen: Cleanup the drivers and modify comments from reviewers] > > Signed-off-by: Bo-Chen Chen > > --- > > [snip] > > > + > > +static void mtk_dp_power_disable(struct mtk_dp *mtk_dp) > > +{ > > + mtk_dp_write(mtk_dp, MTK_DP_TOP_PWR_STATE, 0); > > + > > + mtk_dp_write(mtk_dp, MTK_DP_0034, > > + DA_CKM_CKTX0_EN_FORCE_EN | > > + DA_CKM_BIAS_LPF_EN_FORCE_VAL | > > + DA_CKM_BIAS_EN_FORCE_VAL | > > + DA_XTP_GLB_LDO_EN_FORCE_VAL | > > + DA_XTP_GLB_AVD10_ON_FORCE_VAL); > > Is this clock gating? If so, separate this to ccf driver. > > Regards, > CK > Hello CK, this register is inside dp hardware, so it should not move to ccf driver. BRs, Bo-Chen > > + > > + /* Disable RX */ > > + mtk_dp_write(mtk_dp, MTK_DP_1040, 0); > > + mtk_dp_write(mtk_dp, MTK_DP_TOP_MEM_PD, > > + 0x550 | BIT(FUSE_SEL_SHIFT) | > > BIT(MEM_ISO_EN_SHIFT)); > > +} > > + > >