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Fri, 27 Mar 2026 03:03:44 -0700 (PDT) Received: from [192.168.2.83] ([46.175.183.46]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-487271154d8sm17722575e9.9.2026.03.27.03.03.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 27 Mar 2026 03:03:44 -0700 (PDT) Message-ID: <34f4d05e-9ad5-468d-8c27-0b745b66afbe@redhat.com> Date: Fri, 27 Mar 2026 11:03:42 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH net-next 1/5] dpll: zl3073x: clean up esync get/set and use zl3073x_out_is_ndiv() To: Ivan Vecera , netdev@vger.kernel.org Cc: Arkadiusz Kubalewski , Jiri Pirko , Michal Schmidt , Prathosh Satish , Simon Horman , Vadim Fedorenko , linux-kernel@vger.kernel.org, Conor Dooley , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, Pasi Vaananen References: <20260319174826.7623-1-ivecera@redhat.com> <20260319174826.7623-2-ivecera@redhat.com> Content-Language: en-US From: Petr Oros In-Reply-To: <20260319174826.7623-2-ivecera@redhat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit > Return -EOPNOTSUPP early in esync_get callbacks when esync is not > supported instead of conditionally populating the range at the end. > This simplifies the control flow by removing the finish label/goto > in the output variant and the conditional range assignment in both > input and output variants. > > Replace open-coded N-div signal format switch statements with > zl3073x_out_is_ndiv() helper in esync_get, esync_set and > frequency_set callbacks. > > Signed-off-by: Ivan Vecera > --- > drivers/dpll/zl3073x/dpll.c | 64 ++++++++++++------------------------- > 1 file changed, 20 insertions(+), 44 deletions(-) > > diff --git a/drivers/dpll/zl3073x/dpll.c b/drivers/dpll/zl3073x/dpll.c > index a29f606318f6d..79ef62d69a32d 100644 > --- a/drivers/dpll/zl3073x/dpll.c > +++ b/drivers/dpll/zl3073x/dpll.c > @@ -131,6 +131,12 @@ zl3073x_dpll_input_pin_esync_get(const struct dpll_pin *dpll_pin, > ref_id = zl3073x_input_pin_ref_get(pin->id); > ref = zl3073x_ref_state_get(zldev, ref_id); > > + if (!pin->esync_control || zl3073x_ref_freq_get(ref) == 1) > + return -EOPNOTSUPP; > + > + esync->range = esync_freq_ranges; > + esync->range_num = ARRAY_SIZE(esync_freq_ranges); > + > switch (FIELD_GET(ZL_REF_SYNC_CTRL_MODE, ref->sync_ctrl)) { > case ZL_REF_SYNC_CTRL_MODE_50_50_ESYNC_25_75: > esync->freq = ref->esync_n_div == ZL_REF_ESYNC_DIV_1HZ ? 1 : 0; > @@ -142,17 +148,6 @@ zl3073x_dpll_input_pin_esync_get(const struct dpll_pin *dpll_pin, > break; > } > > - /* If the pin supports esync control expose its range but only > - * if the current reference frequency is > 1 Hz. > - */ > - if (pin->esync_control && zl3073x_ref_freq_get(ref) > 1) { > - esync->range = esync_freq_ranges; > - esync->range_num = ARRAY_SIZE(esync_freq_ranges); > - } else { > - esync->range = NULL; > - esync->range_num = 0; > - } > - > return 0; > } > > @@ -582,8 +577,8 @@ zl3073x_dpll_output_pin_esync_get(const struct dpll_pin *dpll_pin, > struct zl3073x_dpll_pin *pin = pin_priv; > const struct zl3073x_synth *synth; > const struct zl3073x_out *out; > + u32 synth_freq, out_freq; > u8 clock_type, out_id; > - u32 synth_freq; > > out_id = zl3073x_output_pin_out_get(pin->id); > out = zl3073x_out_state_get(zldev, out_id); > @@ -592,17 +587,19 @@ zl3073x_dpll_output_pin_esync_get(const struct dpll_pin *dpll_pin, > * for N-division is also used for the esync divider so both cannot > * be used. > */ > - switch (zl3073x_out_signal_format_get(out)) { > - case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV: > - case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV: > + if (zl3073x_out_is_ndiv(out)) > return -EOPNOTSUPP; > - default: > - break; > - } > > /* Get attached synth frequency */ > synth = zl3073x_synth_state_get(zldev, zl3073x_out_synth_get(out)); > synth_freq = zl3073x_synth_freq_get(synth); > + out_freq = synth_freq / out->div; > + > + if (!pin->esync_control || out_freq == 1) > + return -EOPNOTSUPP; > + > + esync->range = esync_freq_ranges; > + esync->range_num = ARRAY_SIZE(esync_freq_ranges); > > clock_type = FIELD_GET(ZL_OUTPUT_MODE_CLOCK_TYPE, out->mode); > if (clock_type != ZL_OUTPUT_MODE_CLOCK_TYPE_ESYNC) { > @@ -610,11 +607,11 @@ zl3073x_dpll_output_pin_esync_get(const struct dpll_pin *dpll_pin, > esync->freq = 0; > esync->pulse = 0; > > - goto finish; > + return 0; > } > > /* Compute esync frequency */ > - esync->freq = synth_freq / out->div / out->esync_n_period; > + esync->freq = out_freq / out->esync_n_period; > > /* By comparing the esync_pulse_width to the half of the pulse width > * the esync pulse percentage can be determined. > @@ -623,18 +620,6 @@ zl3073x_dpll_output_pin_esync_get(const struct dpll_pin *dpll_pin, > */ > esync->pulse = (50 * out->esync_n_width) / out->div; > > -finish: > - /* Set supported esync ranges if the pin supports esync control and > - * if the output frequency is > 1 Hz. > - */ > - if (pin->esync_control && (synth_freq / out->div) > 1) { > - esync->range = esync_freq_ranges; > - esync->range_num = ARRAY_SIZE(esync_freq_ranges); > - } else { > - esync->range = NULL; > - esync->range_num = 0; > - } > - > return 0; > } > > @@ -660,13 +645,8 @@ zl3073x_dpll_output_pin_esync_set(const struct dpll_pin *dpll_pin, > * for N-division is also used for the esync divider so both cannot > * be used. > */ > - switch (zl3073x_out_signal_format_get(&out)) { > - case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV: > - case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV: > + if (zl3073x_out_is_ndiv(&out)) > return -EOPNOTSUPP; > - default: > - break; > - } > > /* Select clock type */ > if (freq) > @@ -728,9 +708,9 @@ zl3073x_dpll_output_pin_frequency_set(const struct dpll_pin *dpll_pin, > struct zl3073x_dev *zldev = zldpll->dev; > struct zl3073x_dpll_pin *pin = pin_priv; > const struct zl3073x_synth *synth; > - u8 out_id, signal_format; > u32 new_div, synth_freq; > struct zl3073x_out out; > + u8 out_id; > > out_id = zl3073x_output_pin_out_get(pin->id); > out = *zl3073x_out_state_get(zldev, out_id); > @@ -740,12 +720,8 @@ zl3073x_dpll_output_pin_frequency_set(const struct dpll_pin *dpll_pin, > synth_freq = zl3073x_synth_freq_get(synth); > new_div = synth_freq / (u32)frequency; > > - /* Get used signal format for the given output */ > - signal_format = zl3073x_out_signal_format_get(&out); > - > /* Check signal format */ > - if (signal_format != ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV && > - signal_format != ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV) { > + if (!zl3073x_out_is_ndiv(&out)) { > /* For non N-divided signal formats the frequency is computed > * as division of synth frequency and output divisor. > */ LGTM, Reviewed-by: Petr Oros