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[70.187.214.22]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-37955f01d68sm11849406eec.17.2026.11.13.20.16.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 13 Nov 2026 20:16:43 -0800 (PST) Message-ID: <34ffee4c-c5f6-4050-b76c-637fc48d1030@gmail.com> Date: Fri, 13 Nov 2026 20:16:41 -0800 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: ARM BCM53573 SoC hangs/lockups caused by locks/clock/random changes To: Florian Fainelli , Linus Walleij , =?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?= Cc: Peter Zijlstra , Ingo Molnar , Will Deacon , Waiman Long , Boqun Feng , Russell King , Daniel Lezcano , Thomas Gleixner , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, openwrt-devel@lists.openwrt.org, bcm-kernel-feedback-list@broadcom.com References: <92190d04-9b43-47ad-9dd0-4b85bb60f8ef@broadcom.com> Content-Language: en-US From: Florian Fainelli In-Reply-To: <92190d04-9b43-47ad-9dd0-4b85bb60f8ef@broadcom.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Rafal! On 11/29/2023 1:42 PM, Florian Fainelli wrote: > On 11/29/23 13:33, Linus Walleij wrote: >> On Wed, Nov 29, 2023 at 10:20 PM Rafał Miłecki wrote: >> >>> Here comes more interesting experiment though. Putting there: >>> >>> if (!(foo++ % 10000)) { >>>          pr_info("[%s] arm_pm_idle:%ps\n", __func__, arm_pm_idle); >>> } >>> >>> doesn't seem to help. >>> >>> >>> Putting following however seems to make kernel/device stable: >>> >>> if (!(foo++ % 100)) { >>>          pr_info("[%s] arm_pm_idle:%ps\n", __func__, arm_pm_idle); >>> } >> >> That's just too weird. > > It does seem to indicate that idling for too long wrecks havoc, but it > is indeed not making much sense. Not having proper documentation for > this SoC, it is hard to figure out what impact does stopping the ARM CPU > clock has on the rest of the memory subsystem, especially outside of the > CPU. I do not believe that this SoC has any form of PLL clock gating or > pulse skipping. > >> >>> I think I'm just going to assume those chipsets are simply hw broken. >> >> If disabling CPU idle on these altogether stabilize them, then maybe that >> is what we need to do? > > Yes, please try booting with "nohlt" set on the kernel command line and > see how that fares. > > Also useful would be to dump the L2 CTLR and L2 ECTLR, this is a > complete shot in the dark, though was initially wondering if there could > be some retention issues, and would have recommended disabling the L2 > retention policy completely just for testing. > > MRC p15, 1, , c9, c0, 2; > > of particular interest here would be bit at position 0, try to see if > changing it to 1 (3 cycles) or 0 (2 cycles) changes anything. > > MRC p15, 1, , c9, c0, 3; > > the lower bits are reserved, so I would not necessarily expect them to > be mapping to configurable latencies, but if you see non-zero values in > bits [28:0], try changing them to 0 and see if that changes anything. > > Thanks for your persistence! Thankfully now we have MCPs and it did not take look to identify a lead that was actually documented into an internal bug tracker! Would you be able to test this branch: https://github.com/ffainelli/linux/pull/new/rfc/bcm53573-counter-wa -- Florian