From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F8682C1596 for ; Wed, 19 Nov 2025 15:52:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763567539; cv=none; b=ublsgwmoTYmrkeYCtO7ltg9q22JK+FmiBv36Dd35o2iFNjz/h+amELxDpBByP00e9lnazK91LrzNY/tWv1LnZo8vnysuT875pvHG19fC6TTpAKHv+UbEcL8edNfOlW45Yc3bVZkYGfQ99Fj1H89SHU1hulog3Gi3cOpdS8ZOz2o= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763567539; c=relaxed/simple; bh=7FBm2pA3p+MjBgITQg+SdeuwcZfV8pg78x6e3pMzwVs=; h=Date:From:To:cc:Subject:In-Reply-To:Message-ID:References: MIME-Version:Content-Type; b=cYaIQ4/RX0ORI9HB0Tp2bYlxinQTjTDWv0jPlPL4CZ010SKkvgx9CR1QtdfjJ24N9B5y3taXNxJS7V4t5WbRdiJskCOL84J2FE3Hka/QZ3/DgA1gkuhKfTwJa+y72HPleFjMje1WKxQgqiPJxfiO0v4Qs3aPgeinJbmt8GRfWc8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=azXf6kup; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="azXf6kup" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CDBBBC4DDF8; Wed, 19 Nov 2025 15:52:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1763567538; bh=7FBm2pA3p+MjBgITQg+SdeuwcZfV8pg78x6e3pMzwVs=; h=Date:From:List-Id:To:cc:Subject:In-Reply-To:References:From; b=azXf6kuph8YIH/6gTeAN8ASFX4cUDu3oezkVwxE30ue29dK3zM9FbIAkdvFOtBm5U xyic6fky5EGretMReyNxfrEaBBUQpLPJuRpqIx2jef8uos/qZSeqDVQ4yeC4HmYd8R U4PbBPpKn1h1cLKnWLNdUzyAlKz9W1fJ3cjwsvilcYxrzBU3KgHc1qtnyYSqB4ubLf B5sxJAF80/ndhREDDdEXP9hEiptZl6gwmHGen6Tk/hlWHYbEv1UwMfzBlG43lL6CEU xYTCxx7aCexdD+/dL82+sGQkB8yiyW2BtaWqggfAgytg+62dr55OOLZyPdAXmedGAc U5miHI48RhQmg== Date: Wed, 19 Nov 2025 08:52:16 -0700 (MST) From: Paul Walmsley To: patchwork-bot+linux-riscv@kernel.org cc: =?ISO-8859-15?Q?Cl=E9ment_L=E9ger?= , linux-riscv@lists.infradead.org, paul.walmsley@sifive.com, palmer@dabbelt.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, hchauhan@ventanamicro.com, apatel@ventanamicro.com, luxu.kernel@bytedance.com, atishp@atishpatra.org, bjorn@rivosinc.com, cuiyunhui@bytedance.com Subject: Re: [PATCH v8 0/5] riscv: add support for SBI Supervisor Software Events In-Reply-To: <176355541775.758643.18140349571928540394.git-patchwork-notify@kernel.org> Message-ID: <350edd01-56ce-6558-1473-4b9231647e1e@kernel.org> References: <20251105082639.342973-1-cleger@rivosinc.com> <176355541775.758643.18140349571928540394.git-patchwork-notify@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="8323329-1889358478-1763567537=:1438789" This message is in MIME format. The first part should be readable text, while the remaining parts are likely unreadable without MIME-aware tools. --8323329-1889358478-1763567537=:1438789 Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 8BIT To add more context: On Wed, 19 Nov 2025, patchwork-bot+linux-riscv@kernel.org wrote: > This series was applied to riscv/linux.git (for-next) > by Paul Walmsley : > > On Wed, 5 Nov 2025 08:26:32 +0000 you wrote: > > The SBI Supervisor Software Events (SSE) extensions provides a mechanism > > to inject software events from an SBI implementation to supervisor > > software such that it preempts all other supervisor level traps and > > interrupts. This extension is introduced by the SBI v3.0 specification[1]. > > > > Various events are defined and can be send asynchronously to supervisor > > software (RAS, PMU, DEBUG, Asynchronous page fault) from SBI as well > > as platform specific events. Events can be either local (per-hart) or > > global. Events can be nested on top of each other based on priority and > > can interrupt the kernel at any time. > > > > [...] > > Here is the summary with links: > - [v8,1/5] riscv: add SBI SSE extension definitions > https://git.kernel.org/riscv/c/7bba38249b8a > - [v8,2/5] riscv: add support for SBI Supervisor Software Events extension > https://git.kernel.org/riscv/c/b52179e6de7d > - [v8,3/5] drivers: firmware: add riscv SSE support > https://git.kernel.org/riscv/c/5ffe60d26107 > - [v8,4/5] perf: RISC-V: add support for SSE event > https://git.kernel.org/riscv/c/c6f3f04d2a9c > - [v8,5/5] selftests/riscv: add SSE test module > https://git.kernel.org/riscv/c/a123316660af This is a pretty sophisticated series. I was hoping to get more test reports on it and reviews (as Clément requested as well). In the meantime I've pulled them into for-next in the hopes that it might increase the number of potential testers. Am still very much interested in any test reports or additional reviews; if they come in this week, I'll consider rebuilding for-next to add them. - Paul --8323329-1889358478-1763567537=:1438789--