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Sampat" , kvm@vger.kernel.org, x86@kernel.org, linux-kernel@vger.kernel.org Cc: tglx@kernel.org, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, seanjc@google.com, pbonzini@redhat.com, kim.phillips@amd.com, nikunj@amd.com, michael.roth@amd.com, ashish.kalra@amd.com References: <92a1de684bfb5d8633c2de0ed8511f33282a0d70.1791302373.git.prsampat@amd.com> Content-Language: en-US From: Tom Lendacky Autocrypt: addr=thomas.lendacky@amd.com; keydata= xsFNBFaNZYkBEADxg5OW/ajpUG7zgnUQPsMqWPjeAxtu4YH3lCUjWWcbUgc2qDGAijsLTFv1 kEbaJdblwYs28z3chM7QkfCGMSM29JWR1fSwPH18WyAA84YtxfPD8bfb1Exwo0CRw1RLRScn 6aJhsZJFLKyVeaPO1eequEsFQurRhLyAfgaH9iazmOVZZmxsGiNRJkQv4YnM2rZYi+4vWnxN 1ebHf4S1puN0xzQsULhG3rUyV2uIsqBFtlxZ8/r9MwOJ2mvyTXHzHdJBViOalZAUo7VFt3Fb aNkR5OR65eTL0ViQiRgFfPDBgkFCSlaxZvc7qSOcrhol160bK87qn0SbYLfplwiXZY/b/+ez 0zBtIt+uhZJ38HnOLWdda/8kuLX3qhGL5aNz1AeqcE5TW4D8v9ndYeAXFhQI7kbOhr0ruUpA udREH98EmVJsADuq0RBcIEkojnme4wVDoFt1EG93YOnqMuif76YGEl3iv9tYcESEeLNruDN6 LDbE8blkR3151tdg8IkgREJ+dK+q0p9UsGfdd+H7pni6Jjcxz8mjKCx6wAuzvArA0Ciq+Scg hfIgoiYQegZjh2vF2lCUzWWatXJoy7IzeAB5LDl/E9vz72cVD8CwQZoEx4PCsHslVpW6A/6U NRAz6ShU77jkoYoI4hoGC7qZcwy84mmJqRygFnb8dOjHI1KxqQARAQABzSZUb20gTGVuZGFj a3kgPHRob21hcy5sZW5kYWNreUBhbWQuY29tPsLBmQQTAQoAQwIbIwcLCQgHAwIBBhUIAgkK CwQWAgMBAh4BAheAAhkBFiEE3Vil58OMFCw3iBv13v+a5E8wTVMFAmkbaKgFCRZQah8ACgkQ 3v+a5E8wTVPFyg//UYANiuHfxxJET8D6p/vIV0xYcf1SXCG78M+5amqcE/4cCIJWyAT3A1nP zwyQIaIjUlGsXQtNgC1uVteCnMNJCjVQm0nLlJ9IVtXxzRg0QKjuSdZxuL5jrIon4xW9hTJR 94i2v3Fx5UWyP2TB6qZOcB0jgh0l01GHF9/DVJbmQlpvQB4Z1uNv09Q7En6EXi28TSv0Ffd1 p8vKqxwz7CMeAeZpn5i7s1QE/mQtdkyAmhuGD12tNbWzFamrDD1Kq3Em4TIFko0+k5+oQAAf JFaZc1c0D4GtXwvv4y+ssI0eZuOBXapUHeNNVf3JGuF6ZPLNPAe5gMQrmsJinEArVYRQCuDA BZakbKw9YJpGhnSVeCl2zSHcVgXuDs4J2ONxdsGynYv5cjPb4XTYPaE1CZH7Vy1tqma8eErG rcCyP1seloaC1UQcp8UDAyEaBjh3EqvTvgl+SppHz3im0gPJgR9km95BA8iGx9zqDuceATBc +A007+XxdFIsifMGlus0DKPmNAJaLkEEUMedBBxH3bwQ+z8tmWHisCZQJpUeGkwttD1LK/xn KRnu8AQpSJBB2oKAX1VtLRn8zLQdGmshxvsLUkKdrNE6NddhhfULqufNBqul0rrHGDdKdTLr cK5o2dsf9WlC4dHU2PiXP7RCjs1E5Ke0ycShDbDY5Zeep/yhNWLOwU0EVo1liQEQAL7ybY01 hvEg6pOh2G1Q+/ZWmyii8xhQ0sPjvEXWb5MWvIh7RxD9V5Zv144EtbIABtR0Tws7xDObe7bb r9nlSxZPur+JDsFmtywgkd778G0nDt3i7szqzcQPOcR03U7XPDTBJXDpNwVV+L8xvx5gsr2I bhiBQd9iX8kap5k3I6wfBSZm1ZgWGQb2mbiuqODPzfzNdKr/MCtxWEsWOAf/ClFcyr+c/Eh2 +gXgC5Keh2ZIb/xO+1CrTC3Sg9l9Hs5DG3CplCbVKWmaL1y7mdCiSt2b/dXE0K1nJR9ZyRGO lfwZw1aFPHT+Ay5p6rZGzadvu7ypBoTwp62R1o456js7CyIg81O61ojiDXLUGxZN/BEYNDC9 n9q1PyfMrD42LtvOP6ZRtBeSPEH5G/5pIt4FVit0Y4wTrpG7mjBM06kHd6V+pflB8GRxTq5M 7mzLFjILUl9/BJjzYBzesspbeoT/G7e5JqbiLWXFYOeg6XJ/iOCMLdd9RL46JXYJsBZnjZD8 Rn6KVO7pqs5J9K/nJDVyCdf8JnYD5Rq6OOmgP/zDnbSUSOZWrHQWQ8v3Ef665jpoXNq+Zyob pfbeihuWfBhprWUk0P/m+cnR2qeE4yXYl4qCcWAkRyGRu2zgIwXAOXCHTqy9TW10LGq1+04+ LmJHwpAABSLtr7Jgh4erWXi9mFoRABEBAAHCwXwEGAEKACYCGwwWIQTdWKXnw4wULDeIG/Xe /5rkTzBNUwUCaRto5wUJFlBqXgAKCRDe/5rkTzBNUw4/EAClG106SeHXiJ+ka6aeHysDNVgZ 8pUbB2f8dWI7kzD5AZ5kLENnsi1MzJRYBwtg/vVVorZh6tavUwcIvsao+TnV57gXAWr6sKIc xyipxRVEXmHts22I6vL1DirLAoOLAwWilkM+JzbVE3MMvC+cCVnMzzchrMYDTqn1mjCCwiIe u5oop+K/RgeHYPsraumyA9/kj8iazrLM+lORukCNM7+wlRClcY8TGX+VllANym9B6FMxsJ5z Q7JeeXIgyGlcBRME+m3g40HfIl+zM674gjv2Lk+KjS759KlX27mQfgnAPX4tnjLcmpSQJ77I Qg+Azi/Qloiw7L/WsmxEO5ureFgGIYDQQUeM1Qnk76K5Z3Nm8MLHtjw3Q7kXHrbYn7tfWh4B 7w5Lwh6NoF88AGpUrosARVvIAd93oo0B9p40Or4c5Jao1qqsmmCCD0dl7WTJCboYTa2OWd99 oxS7ujw2t1WMPD0cmriyeaFZnT5cjGbhkA+uQGuT0dMQJdLqW3HRwWxyiGU/jZUFjHGFmUrj qFAgP+x+ODm6/SYn0LE0VLbYuEGfyx5XcdNnSvww1NLUxSvuShcJMII0bSgP3+KJtFqrUx9z l+/NCGvn/wMy6NpYUpRSOmsqVv0N71LbtXnHRrJ42LzWiRW2I5IWsb1TfdMAyVToHPNaEb0i WiyqywZI5g== In-Reply-To: <92a1de684bfb5d8633c2de0ed8511f33282a0d70.1791302373.git.prsampat@amd.com> Content-Type: text/plain; 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Sampat wrote: > Enhanced SMT Protection requires every VMSA to carry the vCPU's identity > and the mask of SMT siblings it may co-run with. The guest builds the > VMSA itself when bringing up an AP, so populate both fields there, before > the page is turned into a VMSA and while it is still writable. > > Fully set the sibling mask so that all threads of the same guest trust > each other. > > Signed-off-by: Pratik R. Sampat Minor comment below, but otherwise: Reviewed-by: Tom Lendacky > --- > v1..v2: > * Add ESMTP to SNP_FEATURES_IMPL and SNP_FEATURES_IMPL_REQ > --- > arch/x86/boot/compressed/sev.c | 6 ++++-- > arch/x86/coco/sev/core.c | 13 +++++++++++++ > arch/x86/include/asm/msr-index.h | 4 +++- > 3 files changed, 20 insertions(+), 3 deletions(-) > > diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c > index c6512f2ea31e..4e0fa5a5f70b 100644 > --- a/arch/x86/boot/compressed/sev.c > +++ b/arch/x86/boot/compressed/sev.c > @@ -188,7 +188,8 @@ bool sev_es_check_ghcb_fault(unsigned long address) > MSR_AMD64_SNP_RESERVED_BIT13 | \ > MSR_AMD64_SNP_RESERVED_BIT15 | \ > MSR_AMD64_SNP_SECURE_AVIC | \ > - MSR_AMD64_SNP_RESERVED_BITS19_22 | \ > + MSR_AMD64_SNP_ESMT_PROT | \ > + MSR_AMD64_SNP_RESERVED_BITS20_22 | \ > MSR_AMD64_SNP_RESERVED_MASK) > > #ifdef CONFIG_AMD_SECURE_AVIC > @@ -204,7 +205,8 @@ bool sev_es_check_ghcb_fault(unsigned long address) > */ > #define SNP_FEATURES_IMPL (MSR_AMD64_SNP_DEBUG_SWAP | \ > MSR_AMD64_SNP_SECURE_TSC | \ > - SNP_FEATURE_SECURE_AVIC) > + SNP_FEATURE_SECURE_AVIC | \ > + MSR_AMD64_SNP_ESMT_PROT) > > u64 snp_get_unsupported_features(u64 status) > { > diff --git a/arch/x86/coco/sev/core.c b/arch/x86/coco/sev/core.c > index cc292d7c6fd1..730cff2700d4 100644 > --- a/arch/x86/coco/sev/core.c > +++ b/arch/x86/coco/sev/core.c > @@ -89,6 +89,7 @@ static const char * const sev_status_feat_names[] = { > [MSR_AMD64_SNP_VMSA_REG_PROT_BIT] = "VMSARegProt", > [MSR_AMD64_SNP_SMT_PROT_BIT] = "SMTProt", > [MSR_AMD64_SNP_SECURE_AVIC_BIT] = "SecureAVIC", > + [MSR_AMD64_SNP_ESMT_PROT_BIT] = "ESMTProt", > [MSR_AMD64_SNP_IBPB_ON_ENTRY_BIT] = "IBPBOnEntry", > }; > > @@ -849,6 +850,18 @@ static int wakeup_cpu_via_vmgexit(u32 apic_id, unsigned long start_ip, unsigned > vmsa->vmpl = snp_vmpl; > vmsa->sev_features = sev_status >> 2; > > + if (cc_platform_has(CC_ATTR_GUEST_SEV_SNP) && > + (sev_status & MSR_AMD64_SNP_ESMT_PROT)) { You're using sev_status for ESMT_PROT, might as well use it for SNP, too, instead of calling cc_platform_has(). Thanks, Tom > + vmsa->vcpu_id = apic_id; > + /* > + * The mask fully set puts every vCPU in one group, so any two > + * of them may be co-resident. A legal ESMTP sibling must > + * also match on ASID, so the sibling of a vCPU in guest mode is > + * always either another vCPU of this same guest or idle. > + */ > + vmsa->vcpu_sibling_mask = U32_MAX; > + } > + > /* Populate AP's TSC scale/offset to get accurate TSC values. */ > if (cc_platform_has(CC_ATTR_GUEST_SNP_SECURE_TSC)) { > vmsa->tsc_scale = snp_tsc_scale; > diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h > index fbcb3313e946..6fd26151d146 100644 > --- a/arch/x86/include/asm/msr-index.h > +++ b/arch/x86/include/asm/msr-index.h > @@ -745,7 +745,9 @@ > #define MSR_AMD64_SNP_SMT_PROT BIT_ULL(MSR_AMD64_SNP_SMT_PROT_BIT) > #define MSR_AMD64_SNP_SECURE_AVIC_BIT 18 > #define MSR_AMD64_SNP_SECURE_AVIC BIT_ULL(MSR_AMD64_SNP_SECURE_AVIC_BIT) > -#define MSR_AMD64_SNP_RESERVED_BITS19_22 GENMASK_ULL(22, 19) > +#define MSR_AMD64_SNP_ESMT_PROT_BIT 19 > +#define MSR_AMD64_SNP_ESMT_PROT BIT_ULL(MSR_AMD64_SNP_ESMT_PROT_BIT) > +#define MSR_AMD64_SNP_RESERVED_BITS20_22 GENMASK_ULL(22, 20) > #define MSR_AMD64_SNP_IBPB_ON_ENTRY_BIT 23 > #define MSR_AMD64_SNP_IBPB_ON_ENTRY BIT_ULL(MSR_AMD64_SNP_IBPB_ON_ENTRY_BIT) > #define MSR_AMD64_SNP_RESV_BIT 24