From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21786C43217 for ; Thu, 24 Nov 2022 15:39:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229715AbiKXPjp (ORCPT ); Thu, 24 Nov 2022 10:39:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55396 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229677AbiKXPjm (ORCPT ); Thu, 24 Nov 2022 10:39:42 -0500 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8FAE26DCD3; Thu, 24 Nov 2022 07:39:41 -0800 (PST) Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2AOD0fmw010871; Thu, 24 Nov 2022 15:39:33 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=message-id : date : mime-version : subject : to : cc : references : from : in-reply-to : content-type : content-transfer-encoding; s=qcppdkim1; bh=mQc0L8cZEGlhu1QSByQkkxeahmkseStXK0uV8bbap98=; b=jue90TkDU/VAEMYOy2J6tLZBgeARjBRHBI/0ZZfxyqfJHdjIF2V2o19Pgv+tv0Rh6Kh4 0sD3v9S16KMpazj5JXcw4qa+cuLHVbj3sTraYUVzd5cmvrtajrQvMdu5I+3a9A7YDobm fL9rKTyCoMnn6JP71UcdTW8aeE7ND+u25Q3QPc5XsZyuSNIbE3zbuYxIa0fUnF1nKjQk 6kRYe6KdvM5M6ujUqQlTI0V+lSv7D4RKOFXvALLZ95RtwUaM35usXMkyazzzhUi6Ri/H 6gLzKOO1+kNeV385kMxGkCo3JrdEjs89Um+NkRoGDfrdvGuR3h15TUX409JwNVAr+3wz 8Q== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3m21mb9q0f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 24 Nov 2022 15:39:33 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 2AOFdVVJ019826 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 24 Nov 2022 15:39:31 GMT Received: from [10.50.29.33] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Thu, 24 Nov 2022 07:39:27 -0800 Message-ID: <351fa466-90cb-b73f-a2a4-749bc3529e22@quicinc.com> Date: Thu, 24 Nov 2022 21:09:20 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.3.2 Subject: Re: [PATCH v2 02/10] arm64: dts: qcom: Add base SM8550 dtsi To: Abel Vesa , Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Neil Armstrong CC: Linux Kernel Mailing List , , References: <20221124135646.1952727-1-abel.vesa@linaro.org> <20221124135646.1952727-3-abel.vesa@linaro.org> From: Sai Prakash Ranjan In-Reply-To: <20221124135646.1952727-3-abel.vesa@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: cYRHJtyrqKAAKp49DMTCPX1LEX59uoRp X-Proofpoint-GUID: cYRHJtyrqKAAKp49DMTCPX1LEX59uoRp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-11-24_11,2022-11-24_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxlogscore=942 lowpriorityscore=0 mlxscore=0 spamscore=0 malwarescore=0 impostorscore=0 priorityscore=1501 bulkscore=0 phishscore=0 clxscore=1011 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2211240116 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 11/24/2022 7:26 PM, Abel Vesa wrote: > Add base dtsi for SM8550 SoC and includes base description of > CPUs, GCC, RPMHCC, UART, interrupt controller, TLMM, reserved > memory, RPMh PD, TCSRCC, ITS, IPCC, AOSS QMP, LLCC, cpufreq, > interconnect, thermal sensor, cpu cooling maps and SMMU nodes > which helps boot to shell with console on boards with this SoC. > > Co-developed-by: Neil Armstrong > Signed-off-by: Neil Armstrong > Signed-off-by: Abel Vesa > --- ... > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = , > + , > + , > + ; This last interrupt must be Hypervisor physical irq(10) and 12 is Hyp virtual irq, so please change it to 10. I guess you got this from downstream but it's not right and they don't boot kernel in EL2. Thanks, Sai