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Subject: Re: [PATCH 1/2] dts: display5: Device tree description of LWN's
 DISPLAY5 board
To: Fabio Estevam <festevam@gmail.com>
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From: =?UTF-8?Q?=c5=81ukasz_Majewski?= <lukma@denx.de>
Organization: DENX
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Date: Wed, 20 Sep 2017 11:45:12 +0200
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Hi Fabio,

> Hi Lukasz,
> 
> On Wed, Sep 20, 2017 at 6:22 AM, Łukasz Majewski <lukma@denx.de> wrote:
> 
>> Could you be more specific here?
>>
>> The 0x80000000 corresponds to IMX_NO_PAD_CTL in pinctrl-imx.c, which
>> prevents from manual GPIO control.
>>
>> The 0x80000000 value is the IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11 (0x020E_0654)
>> config data (16 bits only -> 0x0).
>>
>> Writing 0x0 to this register is perfectly fine for my application.
>>
>>
>> I'm a bit in doubt to what I shall do more?
> 
> As per the Reference Manual, the POR reset for
> IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11 is 0x1b0b0.
> 
> 0x80000000 tells the kernel to not touch this IOMUX and use whatever
> value comes from the bootloader.
> 
> If your bootloader does not touch this register, then you probably
> read 0x1b0b0 from it.
> 
> In this case, please do this instead:
> 
> MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x1b0b0
> 

Ok. Thanks for explanation :-)


-- 
Best regards,

Lukasz Majewski

--

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