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dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Received: from CY5PR12MB6252.namprd12.prod.outlook.com (2603:10b6:930:20::17) by EA3PR12MB178636.namprd12.prod.outlook.com (2603:10b6:303:308::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.569.10; Fri, 30 Oct 2026 11:46:31 +0000 Received: from CY5PR12MB6252.namprd12.prod.outlook.com ([fe80::ab00:d77:6014:64a2]) by CY5PR12MB6252.namprd12.prod.outlook.com ([fe80::ab00:d77:6014:64a2%4]) with mapi id 15.21.0569.009; Fri, 30 Oct 2026 11:46:31 +0000 Message-ID: <354b6a81-b8d8-4394-83aa-2afa13108df7@amd.com> Date: Fri, 30 Oct 2026 17:15:25 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 14/21] soundwire: amd: Preserve lane control bits in amd_sdw_port_enable() To: Lee Jones , Vinod Koul , Bard Liao , Pierre-Louis Bossart , linux-sound@vger.kernel.org, linux-kernel@vger.kernel.org, "Prasad, Prasad" , Mario Limonciello , "Dommati, Sunil-kumar" , Syed Saba Kareem , "N, Poojitha" Cc: stable@vger.kernel.org References: <20261030104840.3361217-1-lee@kernel.org> <20261030104840.3361217-15-lee@kernel.org> Content-Language: en-US From: "Mukunda,Vijendar" In-Reply-To: <20261030104840.3361217-15-lee@kernel.org> Content-Type: text/plain; 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Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ] > > lane_ctrl_ch_en_reg holds both the channel enable mask > (AMD_DPN_CH_EN_CHMASK) and the lane control field > (AMD_DPN_CH_EN_LCTRL) programmed by amd_sdw_transport_params(). When > enable_ch->enable is false, amd_sdw_port_enable() writes 0 to the entire > register instead of clearing only AMD_DPN_CH_EN_CHMASK, wiping out the > configured lane control bits. > > Clear only the AMD_DPN_CH_EN_CHMASK field when disabling port channels. Multi-lane is not supported on any of the platforms handled by this function (ACP6.3, ACP7.0, ACP7.1, ACP7.2). AMD_DPN_CH_EN_LCTRL (bits [2:0]) is never programmed for these platforms, so it always reads back as 0. Writing 0 to the entire register is therefore functionally identical to clearing only AMD_DPN_CH_EN_CHMASK. Upcoming AMD platforms use an entirely different implementation and will not use this code path either. The described bug has no practical impact on any hardware this code runs on, so the Fixes: tag and Cc: stable@vger.kernel.org are not warranted. Please drop this patch. > > Fixes: d8f48fbdfd9a ("soundwire: amd: Add support for AMD Manager driver") > Closes: https://sashiko.dev/#/bug/linux-9a1be49a-7c40-47d3-9260-b933e590c90b > Cc: stable@vger.kernel.org > Signed-off-by: Lee Jones > --- > drivers/soundwire/amd_manager.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/soundwire/amd_manager.c b/drivers/soundwire/amd_manager.c > index a8220235a2ae..9dfcdde3f2f0 100644 > --- a/drivers/soundwire/amd_manager.c > +++ b/drivers/soundwire/amd_manager.c > @@ -706,11 +706,11 @@ static int amd_sdw_port_enable(struct sdw_bus *bus, > * parameters. > */ > dpn_ch_enable = readl(amd_manager->mmio + lane_ctrl_ch_en_reg); > - u32p_replace_bits(&dpn_ch_enable, enable_ch->ch_mask, AMD_DPN_CH_EN_CHMASK); > if (enable_ch->enable) > - writel(dpn_ch_enable, amd_manager->mmio + lane_ctrl_ch_en_reg); > + u32p_replace_bits(&dpn_ch_enable, enable_ch->ch_mask, AMD_DPN_CH_EN_CHMASK); > else > - writel(0, amd_manager->mmio + lane_ctrl_ch_en_reg); > + u32p_replace_bits(&dpn_ch_enable, 0, AMD_DPN_CH_EN_CHMASK); > + writel(dpn_ch_enable, amd_manager->mmio + lane_ctrl_ch_en_reg); > return 0; > } > > -- > 2.56.0.317.g454f8302e1-goog