From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 58156288DB for ; Mon, 10 Feb 2025 19:20:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739215235; cv=none; b=WCN9eE3LO+n+E7FiO6Qc1b9mCdvTrtfrCHdY+j/gr7cF8019qLF1ZlISK7d/VM2TnS62ygnSdvyGXF6ti79v0sjC1BXfDuOJwOhLZ9TAa8oZDg9byae9/tRhde7gjlwjx8JVMYEex3gJJoHplbqBdXNb4ieuj0B0Rtpnkdwj6V8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739215235; c=relaxed/simple; bh=2S8sds+FiM0QeleBbqPHslxZ1ylft5S/XBauMQ/noPc=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=AkAFE9vGJ3tJlNp4I30qZMT66AwbJt/aZUIYuS8A826q2Q+SK6sPw24XMVyqi+CftDV7J+ktJ04cRGL8BdsCX433WW+nap5eVbnPA7sAvwk7UJQTJlVk2YlmBB/tssUxxOUk9fBBBwofId8/tHrXYyJVEiyMA35tXjcIzlYVRPw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=d3onEnb7; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="d3onEnb7" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 51ABgBXm031888 for ; Mon, 10 Feb 2025 19:20:33 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= UHTGfvXpoiSary/QibcMXc8tUfGDgzwkgTomq3eCaA8=; b=d3onEnb7b6F2REdr agGZdVd0ylJuhAB5T1LsBZYP9jou9ZsTxCYsQ7jiqELxet6WR4g7AWTJSYia/CEK /RMJhKmHHDDQXVrrva4Y8rOHaecVIcZKY6AMRMw5Ah09H5aqsDNqA3PeRpxg87eV 4JqHqbTpmwKCj9akV+m7yeBff2yF9YghM2gpAdwCATRTavOSp88Qq+ITX8a1MGCA 3mp2HlSMglmFR2as9gZhW3cgU/NXxNfUrx6aOXT4mWlVXeLr4ZTIB+OxYCz97BxP xQ/VTcJD3DFrDVhrVeFWRyU2E8cvijdrO1AShoCrG5Yp+fGbHfZsqJBGgkk2iV3+ oWOxsA== Received: from mail-qt1-f197.google.com (mail-qt1-f197.google.com [209.85.160.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44qgtk17x5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Mon, 10 Feb 2025 19:20:33 +0000 (GMT) Received: by mail-qt1-f197.google.com with SMTP id d75a77b69052e-47181a14d8bso7682791cf.3 for ; Mon, 10 Feb 2025 11:20:33 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739215232; x=1739820032; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=UHTGfvXpoiSary/QibcMXc8tUfGDgzwkgTomq3eCaA8=; b=UPJVZUF/SUK4suXOLu8jYc316ndPTffV6DlTHTyHe1VK3JKyrB9+wsPjBJnRc1lhuL asqxvhYm8SVu1S+t5yndW1b8ZQrZAc+TcIFBsS3LBkfgnwuzkIu11iF7B3bjzcoqUs8W hl26nAKCp5GHBuFuTSLBtMMLULmX+gqzPe67GUib6tUPntDzoER+mlI8dQRSs/CTgfpu cLWtSDCeU9TKkU6SqDXkcVhi5/Jaa7ZhkwCaLaN99zD6cCP3VcND04exMlp3YaCDMZbr KnjYwUOJGoivz5Svlanj2lYxrYI2TYJe/+6oiwGg9M0iZBl1fI73VNElVEwQDvopqNwE 4bQw== X-Forwarded-Encrypted: i=1; AJvYcCVxKwEu/kHiqLYv7+pmNzagSTaudI/l+hlqT8iagIpJvY9o5Nt2cAJmrjx/VDhFhT6qza1ObljY9S1Ti44=@vger.kernel.org X-Gm-Message-State: AOJu0YyIYFCIDTgpmoV9zAXckZhoxRnqqzDFqf82FCdCPxKNPiHfZhJc P9WS1vpu9YePXcjZ9288xMG/WGLi8uK95MFgYNWikGqvT4093qDsvcCjgW22XSRgHRwJfSzzWKt QWpWEB7wAVQzijVYl3R3dO8wIyVZ3w4pny7WLi4Nglm6mc7zwDNmll+H7V9ZX+7Q= X-Gm-Gg: ASbGnctQpZAIG0QTY3FZivbTXR/6OsRAD09EFN5fZ0PAKzKpbnHdXHyYOLGQxgYZvVT R7yvpBNx5V84rEakk2ZevKcfHEbjeagIYs6Sr/akBndK8+D96yB0vVvNFrTlTNfYEOLjWmVogAz Klc0572ivYgDo/tdYkqJKZsqzzSaEjYvFU34H7dPgU8gXpdzRpmOxXMD3fXKkoV5XiOdBuOFUlK O7rVr4CYHQcf1acxVcc1tqEyRG0PlXV/mzD9jpcGwkdzBpczr91BXOx6zwpB/dsd2VwCamNsiVL b65tY91bB4bne/PHVXIek9tVw15hAPxTYgslvBUh5KdzFRnB6gConhJiMvk= X-Received: by 2002:a05:622a:1c15:b0:471:8a2a:d9b3 with SMTP id d75a77b69052e-4718a2adb82mr41530421cf.3.1739215232118; Mon, 10 Feb 2025 11:20:32 -0800 (PST) X-Google-Smtp-Source: AGHT+IGhPZhlsQZyrDwqBCWlfYeWNtHXkddUkvcf5DV4cGq6f1WRrWGhD5y1vSBMq6awgol6oyxogA== X-Received: by 2002:a05:622a:1c15:b0:471:8a2a:d9b3 with SMTP id d75a77b69052e-4718a2adb82mr41530101cf.3.1739215231617; Mon, 10 Feb 2025 11:20:31 -0800 (PST) Received: from [192.168.65.90] (078088045245.garwolin.vectranet.pl. [78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab7a58abd76sm549411266b.26.2025.02.10.11.20.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 10 Feb 2025 11:20:31 -0800 (PST) Message-ID: <354f8710-a5ec-47b5-bcfa-bff75ac3ca71@oss.qualcomm.com> Date: Mon, 10 Feb 2025 20:20:27 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/5] arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 SoC To: Dmitry Baryshkov , Nitin Rawat Cc: Melody Olvera , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Alim Akhtar , Avri Altman , Bart Van Assche , Bjorn Andersson , Andy Gross , Konrad Dybcio , Satya Durga Srinivasu Prabhala , Trilok Soni , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Manish Pandey References: <20250113-sm8750_ufs_master-v1-0-b3774120eb8c@quicinc.com> <20250113-sm8750_ufs_master-v1-4-b3774120eb8c@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: oFbimpMNmL8tBsGbx0SP163m51BiE4fU X-Proofpoint-ORIG-GUID: oFbimpMNmL8tBsGbx0SP163m51BiE4fU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-10_10,2025-02-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 suspectscore=0 phishscore=0 impostorscore=0 adultscore=0 clxscore=1015 mlxscore=0 malwarescore=0 bulkscore=0 lowpriorityscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502100156 On 8.02.2025 11:06 PM, Dmitry Baryshkov wrote: > On Sun, Feb 09, 2025 at 12:47:56AM +0530, Nitin Rawat wrote: >> >> >> On 1/14/2025 4:22 PM, Dmitry Baryshkov wrote: >>> On Mon, Jan 13, 2025 at 01:46:27PM -0800, Melody Olvera wrote: >>>> From: Nitin Rawat >>>> >>>> Add UFS host controller and PHY nodes for SM8750 SoC. >>>> >>>> Co-developed-by: Manish Pandey >>>> Signed-off-by: Manish Pandey >>>> Signed-off-by: Nitin Rawat >>>> Signed-off-by: Melody Olvera >>>> --- [...] >>> Use OPP table instead >> >> Currently, OPP is not enabled in the device tree for any previous targets. I > > Excuse me? ufs_opp_table is present on SM8250, SM8550 and SDM845 (and > QCS615). So this is not correct > >> plan to enable OPP in a separate patch at a later stage. This is because >> there is an ongoing patch in the upstream that aims to enable multiple-level >> clock scaling using OPP, which may introduce changes to the device tree >> entries. To avoid extra efforts, I intend to enable OPP once that patch is >> merged. > > Whatever changes are introduced, old DT must still continue to work. > There is no reason to use legacy freq-table-hz if you can use OPP table. > >> Please let me know if you have any concerns. Go ahead with the OPP table. freq-table-hz is ancient and doesn't describe e.g. the required RPMh levels for core clock frequencies. You should then drop required-opps from the UFS node. >>>> + >>>> + resets = <&gcc GCC_UFS_PHY_BCR>; >>>> + reset-names = "rst"; >>>> + >>>> + >>>> + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS >>>> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, >>>> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >>>> + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; >>> >>> Shouldn't cpu-ufs be ACTIVE_ONLY? >> >> As per ufs driver implementation, Icc voting from ufs driver is removed as >> part of low power mode (suspend or clock gating) and voted again in >> resume/ungating path. Hence TAG_ALWAYS will have no power concern. >> All previous targets have the same configuration. > > arch/arm64/boot/dts/qcom/qcs615.dtsi: &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; > > It might be a mistake for that target though. Your explanation sounds > fine to me. Let's use QCOM_ICC_TAG_ACTIVE_ONLY for the CPU path to clear up confusion. Toggling it from the driver makes sense for UFS-idling-while-CPUs-are-online cases and accidentally also does what RPMh does internally in the other case. Konrad