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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5d99008c3b5sm641951a12.12.2025.01.09.05.57.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 09 Jan 2025 05:57:39 -0800 (PST) Message-ID: <356986fa-e66c-4e78-ab92-2593b037ab9a@oss.qualcomm.com> Date: Thu, 9 Jan 2025 14:57:35 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC 1/4] drm/msm/adreno: Add speedbin support for X1-85 To: Akhil P Oommen , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Srinivas Kandagatla Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <20250109-x1e-speedbin-b4-v1-0-009e812b7f2a@quicinc.com> <20250109-x1e-speedbin-b4-v1-1-009e812b7f2a@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250109-x1e-speedbin-b4-v1-1-009e812b7f2a@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: LROuzhqne4FWVuWelIhyhjG12AFuO2fU X-Proofpoint-GUID: LROuzhqne4FWVuWelIhyhjG12AFuO2fU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 malwarescore=0 mlxlogscore=999 spamscore=0 impostorscore=0 priorityscore=1501 clxscore=1015 adultscore=0 phishscore=0 bulkscore=0 lowpriorityscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501090112 On 8.01.2025 11:42 PM, Akhil P Oommen wrote: > Adreno X1-85 has an additional bit which is at a non-contiguous > location in qfprom. Add support for this new "hi" bit along with > the speedbin mappings. > --- > drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 5 +++++ > drivers/gpu/drm/msm/adreno/adreno_gpu.c | 15 ++++++++++++++- > 2 files changed, 19 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > index 0c560e84ad5a53bb4e8a49ba4e153ce9cf33f7ae..e2261f50aabc6a2f931d810f3637dfdba5695f43 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > @@ -1412,6 +1412,11 @@ static const struct adreno_info a7xx_gpus[] = { > .gmu_cgc_mode = 0x00020202, > }, > .address_space_size = SZ_256G, > + .speedbins = ADRENO_SPEEDBINS( > + { 0, 0 }, > + { 263, 1 }, > + { 315, 0 }, > + ), > .preempt_record_size = 4192 * SZ_1K, > }, { > .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */ > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c > index 75f5367e73caace4648491b041f80b7c4d26bf89..7b31379eff444cf3f8ed0dcfd23c14920c13ee9d 100644 > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c > @@ -1078,7 +1078,20 @@ void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem) > > int adreno_read_speedbin(struct device *dev, u32 *speedbin) > { > - return nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin); > + u32 hi_bits = 0; > + int ret; > + > + ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin); > + if (ret) > + return ret; > + > + /* Some chipsets have MSB bits (BIT(8) and above) at a non-contiguous location */ > + ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin_hi", &hi_bits); > + if (ret != -ENOENT) > + return ret; > + > + *speedbin |= (hi_bits << 8); Now that we're overwriting speedbin, we should probably have some checks in order to make sure somebody passing a too-wide cell to one of these won't result in cripplingly-untraceable value corruption I guess we could just introduce nvmem_cell_read_variable_le_u8() and call it a day? Konrad