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(119.65.249.123) by 192.168.10.159 with ESMTP; 21 Jul 2025 13:32:00 +0900 X-Original-SENDERIP: 119.65.249.123 X-Original-SENDERCOUNTRY: KR, South Korea X-Original-MAILFROM: hgkim05@coasia.com X-Original-RCPTTO: krzk@kernel.org, ksk4725@coasia.com, jesper.nilsson@axis.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, alim.akhtar@samsung.com, linus.walleij@linaro.org, tomasz.figa@gmail.com, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, ravi.patel@samsung.com, smn1196@coasia.com, kenkim@coasia.com, pjsin865@coasia.com, gwk1013@coasia.com, mingyoungbo@coasia.com, pankaj.dubey@samsung.com, shradha.t@samsung.com, inbaraj.e@samsung.com, swathi.ks@samsung.com, hrishikesh.d@samsung.com, dj76.yang@samsung.com, hypmean.kim@samsung.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev Message-ID: <35756293677efc07ce4de4d110d9e9b24ec83fcc.camel@coasia.com> Subject: Re: [PATCH 04/16] clk: samsung: artpec-8: Add initial clock support From: Hakyeong Kim To: Krzysztof Kozlowski , ksk4725@coasia.com, Jesper Nilsson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Linus Walleij , Tomasz Figa , Catalin Marinas , Will Deacon , Arnd Bergmann , Ravi Patel , SungMin Park Cc: kenkim , Jongshin Park , GunWoo Kim , GyoungBo Min , Pankaj Dubey , Shradha Todi , Inbaraj E , Swathi K S , Hrishikesh , Dongjin Yang , Sang Min Kim , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev Date: Mon, 21 Jul 2025 13:32:01 +0900 In-Reply-To: <48677b18-3936-464a-a581-26a44ef76c80@kernel.org> References: <20250710002047.1573841-1-ksk4725@coasia.com> <20250710002047.1573841-5-ksk4725@coasia.com> <48677b18-3936-464a-a581-26a44ef76c80@kernel.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.44.4-0ubuntu2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Thu, 2025-07-10 at 09:12 +0200, Krzysztof Kozlowski wrote: > On 10/07/2025 02:20, ksk4725@coasia.com=C2=A0wrote: > > From: Hakyeong Kim > >=20 > > Add initial clock support for ARTPEC-8 SoC which is required > > for enabling basic clock management. > >=20 > > Add clock support for below CMU block in ARTPEC-8 SoC: > > =C2=A0- CMU_IMEM > >=20 > > Signed-off-by: Ravi Patel > > Signed-off-by: Hakyeong Kim > > --- > > =C2=A0drivers/clk/samsung/Kconfig=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |= =C2=A0 8 ++++ > > =C2=A0drivers/clk/samsung/Makefile=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2= =A0 1 + > > =C2=A0drivers/clk/samsung/clk-artpec8.c | 62 > > +++++++++++++++++++++++++++++++ > > =C2=A03 files changed, 71 insertions(+) > > =C2=A0create mode 100644 drivers/clk/samsung/clk-artpec8.c > >=20 > > diff --git a/drivers/clk/samsung/Kconfig > > b/drivers/clk/samsung/Kconfig > > index 76a494e95027..289591b403ad 100644 > > --- a/drivers/clk/samsung/Kconfig > > +++ b/drivers/clk/samsung/Kconfig > > @@ -13,6 +13,7 @@ config COMMON_CLK_SAMSUNG > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0select EXYNOS_5420_COMM= ON_CLK if ARM && SOC_EXYNOS5420 > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0select EXYNOS_ARM64_COM= MON_CLK if ARM64 && ARCH_EXYNOS > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0select TESLA_FSD_COMMON= _CLK if ARM64 && ARCH_TESLA_FSD > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0select ARTPEC8_COMMON_CLK if= ARM64 && ARCH_ARTPEC8 >=20 > Here and: >=20 > > =C2=A0 > > =C2=A0config S3C64XX_COMMON_CLK > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0bool "Samsung S3C64xx c= lock controller support" if > > COMPILE_TEST > > @@ -102,3 +103,10 @@ config TESLA_FSD_COMMON_CLK > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0help > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 Support for the = clock controller present on the Tesla FSD > > SoC. > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 Choose Y here on= ly if you build for this SoC. > > + > > +config ARTPEC8_COMMON_CLK >=20 > here, place it before EXYNOS_3250_COMMON_CLK. Ok, I will reorder macros in alphabatical order. Thanks, Hakyeong Kim >=20 > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0bool "Axis ARTPEC-8 clock co= ntroller support" if > > COMPILE_TEST > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0depends on COMMON_CLK_SAMSUN= G > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0help >=20 >=20 >=20 > Best regards, > Krzysztof